Posted Jun 6, 2011, by Thomas Bollaert
Last night, in his traditional DAC-opening presentation, Gary Smith addressed the crowd with a loud and clear message about the cost of doing hardware design. Design costs are steadily increasing and this is draining life and blood out of the industry. When chip design costs reach $25M, VCs stop funding start-ups. When costs reach $50M, continued Gary Smith, even IDMs struggle to afford ASIC developments.
So … Read More
Tags:
cost,
DAC,
ASIC,
High-Level Synthesis,
How-to,
esl,
Gary Smith
Posted Oct 26, 2009, by Thomas Bollaert
In a recent presentation at the Mentor User2User conference in Dallas, TI’s Karl Renner gave a very detailed presentation on how he used Catapult C to design a set-top-box IP. With only two engineers working on a tight 6 months schedule, Catapult C proved a necessity to complete the project in time.
Karl Renner works as a systems engineer at Texas Instruments in Dallas and over the past 12 years he … Read More
Tags:
Catapult C Synthesis,
High-Level Synthesis,
ASIC,
User Testimonial