Posted Apr 25, 2011, by Thomas Bollaert
In my last two posts, I introduced the question that proved the most challenging in the HLS Bluebook quiz (here) and presented some fundamental concepts about loop unrolling and loop pipelining and explained why answer 2 was not the right one (here).
Let’s now see what happens in the case of answer 1, when we unroll LOOP0 by 4 and pipeline the design with II=1.
Partially unrolling by 4 means … Read More
Tags:
High-Level Synthesis,
Unrolling,
Bluebook,
C synthesis,
HLS,
ANSI C++,
Loop,
Pipelining,
How-to,
Learning
Posted Apr 5, 2011, by Thomas Bollaert
“In recent times, ESL design methodologies have been the talk of the semiconductor design community and have found increasing acceptance. Most of the recent publications have given information on design flow needs and an high level overview of the (C/C++/SystemC) based high level synthesis design process using a small block level design scenario. Although productivity benefits for ESL methodologies … Read More
Tags:
RTL,
OFDM,
STMicroelectronics,
C synthesis,
Catapult C,
ANSI C++,
User Testimonial,
FFT,
Full-Chip,
High-Level Synthesis,
Control-Logic Synthesis,
DesignCon
Posted Mar 7, 2011, by Thomas Bollaert
Good news for the industry: the DATE (Design, Automation, and Test in Europe) conference is back to growth. And perhaps it is not a surprise given that this year the event is being held in Grenoble. With its great views on the snowy Alps, Grenoble is emerging has the major hub of the electronic and semiconductor industry in Europe.
3D ICs, Low-power, ESL… The rich conference program covers all hot … Read More
Tags:
C synthesis,
High-Level Synthesis,
Bluebook,
User Testimonial,
STMicroelectronics,
Tutorial