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Posts tagged with 'TSMC'

Mentor ESL in TSMC Reference Flow 12

Posted Jun 6, 2011, by Thomas Bollaert

One year ago, I was writing about the inclusion of Mentor ESL in the TSMC Reference Flow 11, and why the endorsement of system-level design and high-level synthesis by the world’s leading foundry was a telling sign of maturity for ESL. Since this first major milestone, TSMC and Mentor haven’t remained idle, on the contrary. Both parties teamed-up to take this first ESL flow to a whole new … Read More

Tags: Vista, DAC, esl, Catapult C, TSMC, Verification, High-Level Synthesis, How-to

SystemC and UVM, one step closer

Posted Feb 28, 2011, by Thomas Bollaert

This morning Intel’s Eric Lish, OSCI chair, kicked-off the North American SystemC User Group collocated at DVCon. In his presentation, Eric covered the evolution of SystemC as well as recent and upcoming milestones. It is quite remarkable to see how much effort went into developing the language and the progress made since its debuts, 12 years ago. 12 years may seem like a very long time, but … Read More

Tags: TSMC, SystemC, UVM