Catapult C Synthesis
Full-Chip High-Level Synthesis
Catapult C Synthesis is a high-level synthesis tool for ASIC and FPGA hardware designers who need to deliver optimal implementations with aggressive time-to-market requirements.
ANSI C++ and SystemC Synthesis
Catapult supports both pure untimed ANSI C++ and SystemC, the two major standard languages for high-level design and synthesis, and produces optimal RTL for complex hierarchical systems comprised of control-logic and algorithmic units.
Precise User Control
Designers precisely control the synthesized hardware implementation by applying high-level constraints managing design aspects such as interface protocols, memory architecture, throughput, latency and low-power transformations.
Production-Quality RTL Generation
Technology-aware synthesis leverages physical information to precisely schedule hardware resources and structure control logic to produce superior designs and predictable timing closure.
Interactive Analysis and Optimization
Using the comprehensive set of built-in analysis tools, designers interactively analyze, optimize, and rapidly converge on the optimal solution in terms of power, performance, and area.
Automatic RTL Verification
The fully automated verification flow includes linting and code coverage of the input source code and push-button simulation of the generated RTL, for a faster path to verified RTL.
Benefits
High-level synthesis for any design, for every designer
With Catapult C Synthesis, full hierarchical systems comprised of both control blocks and algorithmic units are implemented automatically, eliminating the typical coding errors and bugs introduced by manual flows. By speeding time to RTL and automating the generation of bug-free RTL, the Catapult C Synthesis tool significantly reduces the time to verified RTL.
Benefits
Dramatically shortens the design cycle
- Correct-by-construction designs
- Error-free RTL generation
- Zero iterations at the RTL
Immediate and measurable benefits
- Fastest path to verified RTL
- More gates produced per engineer
- Positive ROI on first design
Tested, proven, adopted worldwide
- #1 market share for past three years
- Hundreds of users and tape-outs
- Certified in TSMC Reference Flow 11
“We believe that Catapult C and high-level synthesis give us an important competitive edge. It is one of many factors in helping us maintain our leadership in the highly competitive imaging market.”
Sustaining the Competitive Edge
RTL design and verification is a lengthy and time-consuming task. By automating it, Catapult empowers design teams to refocus their efforts where it matters most: at the system level. By spending less time coding and investing more time in exploring and optimizing the specification, truly superior and differentiated designs can be achieved. This is why industry leaders rely on Catapult C to sustain their competitive edge.
“We had a tricky corner-case bug that required 20k patterns of simulation data to trigger. While running those patterns took only an hour in the C simulation, and it would have taken almost 960 hours (or 40 days) in RTL simulation.”
Reducing the Verification Effort
IC development schedules are hampered by a single important obstacle: RTL verification and debug. Hardware description languages (HDL’s) were invented more than twenty years ago and fall short in addressing the complexity of today’s systems. As a result, more than half of the development cycle is spent tracking, fixing and verifying bugs. By elevating the abstraction level and generating correct-by-construction RTL code, Catapult C breaks through the verification gridlock and provides an accelerated path to verified RTL.
“The generated RTL is correct by construction and preserves the system designer’s original algorithm intent, it is much easier to verify….Overall, it was possible to reduce the design cycle for some blocks by 70-80%.”
Increasing Design Productivity
By raising the level of abstraction from RTL to the system level, Catapult C offers a significantly more efficient, automated design process than traditional manual coding methods. Working at the system level gives design teams greater flexibility, improved reusability, faster design turnaround and reduced verification time. In closing the gap between system level and implementation, weeks of engineering effort are shortened to just hours or days. Catapult delivers the necessary design productivity gains to solve the economic equation of profitable ASIC design.
Read Article at Chip Design Magazine