Catapult C Synthesis
Full-Chip High-Level Synthesis
Catapult C Synthesis is a high-level synthesis tool for ASIC and FPGA hardware designers who need to deliver optimal implementations with aggressive time-to-market requirements.
ANSI C++ and SystemC Synthesis
Catapult supports both pure untimed ANSI C++ and SystemC, the two major standard languages for high-level design and synthesis, and produces optimal RTL for complex hierarchical systems comprised of control-logic and algorithmic units.
Precise User Control
Designers precisely control the synthesized hardware implementation by applying high-level constraints managing design aspects such as interface protocols, memory architecture, throughput, latency and low-power transformations.
Production-Quality RTL Generation
Technology-aware synthesis leverages physical information to precisely schedule hardware resources and structure control logic to produce superior designs and predictable timing closure.
Interactive Analysis and Optimization
Using the comprehensive set of built-in analysis tools, designers interactively analyze, optimize, and rapidly converge on the optimal solution in terms of power, performance, and area.
Automatic RTL Verification
The fully automated verification flow includes linting and code coverage of the input source code and push-button simulation of the generated RTL, for a faster path to verified RTL.
What's New
Catapult gains SystemC, Low Power Support
SystemC Support
Mentor Graphics rolls-out SystemC synthesis, expands Catapult C Synthesis full-chip synthesis capabilities with the efficient handling of complex bus interfaces, SoC interconnects and TLM2.0-based ESL flows.
- Synthesizes SystemC input sources
- Supports cycle-accurate coding style for fine-grain control over design results
- Supports transaction-level modeling and ESL flows
- Supports complex buses and SoC interconnects
- Reads in legacy synthesizable SystemC IP descriptions
- Integrates with Mentor Graphics’ Vista platform
TSMC-Qualified
Catapult C Synthesis is now included in the TSMC Reference Flow 11.
- TSMC-qualified 40nm and 65nm low power process synthesis libraries for Catapult C Synthesis
- Integration of TSMC’s Memory Compiler in Catapult C Synthesis
Low Power Support
With its new built-in low power optimizations, Catapult C Synthesis automates prevailing low-power design technique and delivers unrivalled power reduction.
- Fully automated multi-level clock-gating providing near perfect clock gating
- Dynamic power management interfaces
- Reduces power consumption by an average 40%
Control-Logic Support
Catapult C added support for control-logic synthesis. It is the first unified solution that lets designers model, verify, and synthesize complex mixes of control and algorithmic units from a single ANSI C++ source.
- Supports synchronous reactive systems from pure C++
- Dedicated QoR optimizations for optimal control logic timing and area
- Enables mixing data-driven algorithmic blocks with clock-driven control units