Catapult C Synthesis
Full-Chip High-Level Synthesis
Catapult C Synthesis is a high-level synthesis tool for ASIC and FPGA hardware designers who need to deliver optimal implementations with aggressive time-to-market requirements.
ANSI C++ and SystemC Synthesis
Catapult supports both pure untimed ANSI C++ and SystemC, the two major standard languages for high-level design and synthesis, and produces optimal RTL for complex hierarchical systems comprised of control-logic and algorithmic units.
Precise User Control
Designers precisely control the synthesized hardware implementation by applying high-level constraints managing design aspects such as interface protocols, memory architecture, throughput, latency and low-power transformations.
Production-Quality RTL Generation
Technology-aware synthesis leverages physical information to precisely schedule hardware resources and structure control logic to produce superior designs and predictable timing closure.
Interactive Analysis and Optimization
Using the comprehensive set of built-in analysis tools, designers interactively analyze, optimize, and rapidly converge on the optimal solution in terms of power, performance, and area.
Automatic RTL Verification
The fully automated verification flow includes linting and code coverage of the input source code and push-button simulation of the generated RTL, for a faster path to verified RTL.
Catapult C Synthesis Overview
Reduce the Time to Verified RTL
Traditional hardware design methods that require hand-written RTL development and debugging are too time-consuming and error prone for today’s complex designs. Catapult C Synthesis empowers designers to use industry standard ANSI C++ and SystemC to describe functional intent and move up to a more productive abstraction level. From these high-level descriptions, Catapult C Synthesis generates production quality RTL.
- Synthesizes ANSI C++ and SystemC to production quality RTL
- Targets algorithms, control-logic and interfaces for full-chip synthesis
- Dramatically shortens the path to verified RTL
9th ESL Symposium Panel Discussion at DAC 2011
Technology Overview: Executives from Intel, ARM, Freescale, ST and Mentor will examine the industry-wide move to ESL by highlighting the views and experiences of executives from leading semiconductor, IP and EDA companies. View Technology Overview
High-Level Synthesis Blue Book
Michael Fingeroff’s High-Level Synthesis Blue Book presents the most effective C++ synthesis coding style for achieving high quality RTL. Learn more
High-Level Synthesis from ANSI C++ and SystemC
Catapult offers support both for pure untimed ANSI C++ and for SystemC, the two major standard languages for high-level design and synthesis. The untimed nature of C++ makes it the best choice for architectural design and verification at the most abstract level, and SystemC is effective for the finer control desired for synthesis of complex control logic, such as bus interfaces and SoC interconnects.
Control-logic, Datapath and Hierarchial Interconnects
Catapult is the first solution that lets designers model, verify, and synthesize complex mixes of control and algorithmic units from a single high-level model. The tool provides dedicated support and optimizations for control-logic, datapath and interconnects, making it suitable for any type of design. With Catapult users can scale with confidence from single block designs to large-scale multi-block projects, and by doing so, tackle the design complexity of complete systems with full-chip synthesis capabilities.
Front-to-Back, Fully Automated Verification
Catapult integrates a robust and fully automated verification flow, helping designers confidently synthesize their designs and easily validate the correctness of the generated RTL. Starting with the input model, Catapult automatically performs linting and static code checks to catch potential errors and improve the model. Catapult also provides code coverage reports and performs runtime checks, helping designers achieve a higher degree of confidence in their C++ and SystemC code. After the RTL has been synthesized, Catapult automates a complete verification infrastructure reusing the original C++ or SystemC testbench to exercise the generated RTL.
Interactive Micro-Architecture Analysis and Optimization
Catapult combines automation with specific high-level constraints so designers can precisely control the hardware implementation and interactively converge on significantly better quality designs in less time. Results are displayed in a choice of X-Y plots, bar charts, tables, and schematic views. Designers quickly make informed decisions in terms of power, area, and performance to deliver the optimal balance of these features.
Interface Synthesis
Interfaces and their properties have a determinant impact on the performance and quality of a design. For that matter, Catapult is fully geared to help designers make the best interface decisions and build them optimally. The tool accommodates the needs of both architects seeking the best timing and bandwidth and designers needing to implement them most efficiently.
Low-Power Exploration and Optimization
Catapult C Synthesis fully automates highly efficient, low power design techniques; such as multi-level clock gating, memory access optimization, intelligent resource sharing, and multiple clock domains. The tool thoroughly analyzes and optimizes RTL netlists to reduce power consumption, working on a per-register basis to maximize power savings.
Predictable Timing Closure
Catapult features technology-aware scheduling and allocation heuristics to produce superior designs and predictable timing closure in the physical design stage. Catapult C Library Builder collects detailed characterization data from the downstream RTL synthesis tools with specific target technology libraries. This allows Catapult to precisely schedule hardware resources, chain operators, infer multicycle components, and quickly provide accurate area, latency, and throughput estimates without spending costly time and effort going through RTL synthesis.