Catapult C Synthesis

11/20/2009

One user's 5 week eval of CatapultC vs. hand coded RTL

“Unfrozen Caveman Lawyer” shares his experience with Catapult C and explains how he reduced project time by 40% and design area by 29% on his first usage of the tool.

7/24/2009

My Cheesy Must See List at DAC 2009

Catapult C Synthesis makes John Cooley's #1 spot on what to see at DAC

7/14/2009

I Sense A Tremor In The Force

John Cooley writes "From that one US hands-on CatapultC user story, 12 out of the 24 most read items in the past 7 months worth of ESNUGs were now about SystemC/C/C++/Bluespec."

5/08/2009

Mentor tells Synfora get CatC facts straight

Bryan Bowyer of Mentor Graphics corrects Synfora's facts on Catapult C from a previous ESNUG report.

4/22/2009

A second US-based C synthesis design reports in

A US wireless designer details a 60% time to market time savings using Catapult C.

3/06/2009

A hesitant RTL designer trys out CatapultC design

A first time C user describes how they taped out their first wireless short range communication test block in 40% less time.

2/05/2009

What are the 2 biggest reasons to use High Level Synthesis?

Shawn McCloud from Mentor Graphics shares the results of a blind worldwide survey on using ANSI-C/C++/SystemC-to-RTL synthesis.

12/18/2008

Power Opto and Linting in Catapult C and Spyglass:

Dale Polleck from Atrenta talks about using Spyglass with Catapult C

12/18/2008

Using Calypto SLEC in a Catapult C design Flow

Duncan Mackay from calypto writes about using Formal Sequential Logic Equivalency Checking.

11/20/2008

The first US-based C/C++ chip design I’ve seen

A user writes about their experiences with Catapult C Synthesis technology

10/29/2008

George is wrong; SystemC/C++ tools play nicely with each other

Responses to the SystemC vs C++ vs BSV proprietary solutions allegations.

9/18/2008

Forte Cynthesizer, Mentor Catapult C, Target, Imperas

Users answering John’s call: "What were the 1 or 2 or 3 INTERESTING specific tools that you saw at DAC this year? WHY were they interesting to you?”

5/08/2008

Troublemaker’s Panel

A Video panel of EDA commentators discus numerous topics of interest

“In comparison, using algorithmic synthesis, changes were completed faster with fewer engineering resources than expected. The team could then quickly and successfully port the block to the FPGA environment. Overall, it was possible to reduce the design cycle for some blocks by 70-80%.”

“We've been using CatapultC for C-to-RTL synthesis for about 4 months on a pilot project in the area of wireless short range communications. This was our first experience in C level design, yet we were able tape-out our first test block in 40% less time than we would have needed with our usual RTL flow. The entire project from designing C to fully verified RTL took only about 6 weeks with CatC. In contrast, manually creating and verifying a similar sized block in RTL (30K-40K gates) took us about 10 weeks.”

“Catapult delivers a level of productivity that we are unable to achieve using hand-coded RTL methodologies. The productivity benefits come from automatic RTL creation that eases design exploration, plus verification efficiencies delivered by the C testbench Catapult’s error-free RTL code. As we move to implement more complex designs with Catapult, we routinely observe 5x productivity improvements over manual RTL. This is a very valuable tool for anyone designing wireless hardware.”

“When we started evaluating Catapult C, we quickly realized that we had found a winning solution. However, we had no conception that we would move from using this tool in a beta site evaluation role to using it for mission-critical portions of our design so quickly.”

“…methodologies based on pure ANSI C++ provide the most advantages. Catapult Synthesis starts at pure ANSI C++, the highest level of abstraction, to provide an immediate productivity advantage over both RTL and SystemC-based hardware design methodologies. Catapult gives us total control as we refine our high-level models, allowing us to explore a variety of micro architectures and to arrive at an optimal, high-quality implementation quickly.”

“Using the tool, we were able to start at a higher level of abstraction and produce concise RTL code more quickly than before. Automatically producing ASIC and FPGA hardware from an algorithmic description will enable our hardware designers to spend less time coding details and more time optimizing the more meaningful areas of the design.”

“The Catapult C tool's ability to use pure C code as input fits very well in our design flow, allowing us to automatically generate hardware directly from our untimed C/C++ system models regardless of the target technology. Based on the success of our evaluation, we immediately deployed Catapult C in production design projects.”

“Starting from the most abstract algorithm level, we have experimented with RTL generation from C++ down to the hardware implementation while searching for the best solution for the circuit, all within 5 days as opposed to taking weeks or months if we were handcoding the RTL. It is overwhelming to even consider writing two versions of RTL with several hundred thousand logic gates and to experiment with multiple changes of circuit architecture. It is astounding to us how quickly Catapult C Synthesis can generate RTL with ease.”

“We found Catapult C's quality of results and ease-of-use to be very convincing. Using the tool, we are able to realize the benefits of algorithmic synthesis… Algorithmic synthesis requires far less manual effort, allowing us to specify interfaces and hierarchy using constraints, and instantly target FPGA or ASIC implementations without changing the original pure C++ source.”

“Using our traditional RTL flow, three blocks took approximately nine weeks to design. Once we were up to speed on Catapult C Synthesis, all three blocks were done in three weeks starting from the original untimed C++ source, representing an impressive 3X improvement.”

“We have found that the RTL code generated by Catapult C Synthesis meets Fujitsu's stringent criteria and is applicable for our ASIC design data. By including the Catapult C Synthesis library to our standard ASIC design kit, we will be able to provide our mutual customers with our ASIC development service more efficiently and with lower risk.”

“We have gained a significant 60-percent productivity advantage through Catapult C Synthesis, which enables us to conduct additional design exploration and still deliver our product on time. Verification time was much faster because of Catapult’s pure ANSI C++ input. In addition, the C++ model was 1/3 the size of the RTL description, making it much easier to write and review the code. Finally, Catapult C Synthesis delivered highly accurate area and performance estimations for our designs, which allowed us to make design adjustments in-process so we achieved our area and performance specifications.”

“ST has developed one of the industry’s most advanced system level design flows to manage the increasing complexity of today’s System-on-Chip designs. By integrating best-in-class tool technologies from Agilent, Atrenta, Calypto and Mentor with ST’s own design expertise, our system-level design flows can build chips faster, with higher quality and productivity, allowing our customers to derive the maximum benefit from ST’s advanced chip technologies.”

“Being able to achieve a 31 percent reduction in gate count, which correlates closely to silicon real estate and power consumption, speaks for itself. The cooperation between Mentor Graphics and Ericsson to develop a C-based tool that meets our requirements has been fantastic.”

“By using Catapult C Synthesis and the ASIC library from Fujitsu, we successfully taped out a SoC for our next generation multifunction devices. We would like to continue to use this advanced design flow for developing our ASICs.”

“CatapultC is a very promising tool since it shows that after many years of research, C-based synthesis has reached a mature level in industry. But it also shows that a good understanding of the intended hardware as well as good C code are mandatory to achieve good results. CatapultC is powerful because it enables the designer to transform C-coded algorithms to hardware and evaluate different implementations in terms of their performance and resource requirements very quickly.”

“Catapult C Synthesis is now a proven tool that helps accelerate the development of high quality signal processing hardware. Catapult C libraries are the first high-level synthesis technologies to satisfy our stringent standards and we now want to extend the benefits of high-level synthesis to our customers who need to develop sophisticated next-generation designs as quickly as possible, in particular in Mobile, Telecom and Consumer applications.”

“We were impressed by the results. The fact that we could synthesize our untimed, system-level C/C++ source code with minimal modification played an important role in the success of this project. It provided a precise path from our system-level models all the way to RTL, which allowed us to meet our required design goals in significantly less time.”

“When the RTL is implemented in an FPGA which fails to operate as expected, debugging can take a long time. For example, it can be very difficult to determine if the fault lies in the C language code written by the algorithm developer, or the RTL data created by the hardware designer. Catapult was introduced specifically to eliminate problems in the above conventional IC design process. Management recognized how useful it would be if the algorithm developer could design circuits in C.”

“The new enhancements to Catapult C promise to automate the time-consuming process of SystemC model creation. Automatic SystemC model generation has great potential to accelerate block- and system-level verification, which would enable designers to produce better hardware much faster than before.”