Designing Better Broadband Wireless Algorithms for ASIC

Overview

Broadband wireless solutions companies are one of few bright spots in the 2009 economic forecasts. With next-generation equipment finally hitting or about to hit the market around Ultra-Wideband, WiMAX and 60GHz radios, companies are all vying for an edge. Yet, in these tough economic times, hardware design teams are having to do more with fewer resources. For Catapult C Synthesis wireless customers, Catapult C Synthesis is their competitive advantage for getting to market first with the best solution. Applications such as channel estimation and equalization, forward error correction using turbo coding and LDPC have all been implemented by Catapult C Synthesis customers.

Broadband wireless designs present an interesting set of algorithm modeling, design, and verification challenges. Catapult C Synthesis leverages a C++ based bit-accurate data type language entry to enable rapid validation of algorithm and system architecture concepts. Highly optimized RTL can then be synthesized from the bit-accurate C++, with the confidence that the bit-accurate behavior will be correct-by-construction. The automated verification infrastructure included with Catapult C Synthesis enables co-simulation of the original source C++ testbench and design in conjunction with the newly produced RTL. This eliminates the need for block-level RTL testbench generation, with all the specific pin-level interfacing and timing such efforts entail, reducing your “time to verified RTL” considerably.

What You Will Learn

Learn how C++ and Catapult C Synthesis can accelerate the design, implementation, and verification of complex system-level algorithms.

In this webinar, you will learn about modeling techniques for representing bit-accurate arithmetic in C++ using Mentor Graphics' "Algorithmic C" data types. We will show you through a series of presentation material and examples how untimed "pure" C++ algorithms can be turned into high-performance RTL implementations. You will see how the area, latency, and throughput of an algorithm can be optimized, and RTL code created, in minutes instead of the days or weeks required for VHDL or Verilog coding.

You will experience our integrated verification environment to automatically validate the generated RTL functionality against the original C++ design without any need for the RTL design engineer to create an HDL testbench, or deal with vector capture and synchronization. Powerful system level concepts for streaming data between concurrent hierarchical blocks will be covered to illustrate how high performance hierarchical systems can easily be created with C++ and tuned to meet aggressive throughput requirements.

Who Should View

• ASIC hardware engineers implementing complex algorithms for wireless applications