Changing the hardware design process with High Level Synthesis
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Using High-Level Synthesis (HLS) design groups today are fundamentally changing the way they design hardware as the "traditional" RTL design process is breaking.
Duration: 16:07
Tags: High-Level Synthesis
Products: Catapult C Synthesis
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Details
Overview
RTL design tools have significantly improved over the last 15 years. However, we are using the same design methodology and processes to design a 4G broadband modem or H264 decoder as was employed to design a GSM phone or VGA graphics card.
Using High-Level Synthesis (HLS) design groups today are fundamentally changing the way they design hardware as the "traditional" RTL design process is breaking.
This webinar will discuss a 3rd party survey on the motivations for changing the H/W design process to address such issues as RTL design verification, algorithm development schedules, and to cope with the ever increasing design complexity.
We will outline the hardware design process with HLS, and demonstrate how hardware IP is designed at a higher level of abstraction.
Finally, we will illustrate by example the benefits customer have gained by changing the way they do hardware design by adopting HLS.
What You Will Learn
- How HLS reduces RTL design & verification.
- The H/W design process with High-Level Synthesis.
- How HLS reduces the overall development schedule.
About the Presenter
Alex Grove
Alex Grove has over 14 years experience working in the EDA industry. Alex has worked for Synopsys, ARM, and Synplicity and now works for Mentor Graphics as part of the European organisation.
Alex has extensive experience in Synthesis for ASIC and FPGA as well as a very broad knowledge of the EDA industry. After graduating from Aston University with a honors degree in Electronic Engineering and Computer Science, Alex joined Synopsys Northern Europe working on Synthesis and Test.
While working at Synplicity, Alex was a technical specialist for Synplicity’s ASIC product line and supported the FPGA synthesis products. To date, Alex has been working on Mentor’s high level synthesis product ‘Catapult’.
Who Should View
- RTL Designers
- Algorithm & dsp engineers
- System Architects
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