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ESL Simulation with Veloce Hardware Emulation

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Overview

It's often desirable to co-simulate abstract high-level descriptions with RTL blocks. This eliminates the task of creating ESL models for legacy RTL that lies outside the design exploration space and is not subject to change. Running the legacy RTL on the Veloce hardware emulator in tandem with high-level descriptions running in Vista permits full chip verification without sacrificing performance. This session presents an overview of the Veloce emulator and its integration with Vista.

What You Will Learn

  • How ESL tools help shorten the total design cycle
  • The latest advancements in reaching verification coverage
  • How to enhance your productivity with state-of-the art ESL technology

Who Should Attend

  • Hardware designers
  • ESL engineers
  • Verification engineers

About the Presenter

Presenter Image Jim Kenney

Jim Kenney has 30 years of simulation experience including hardware emulation and HW/SW co-simulation. He’s worked as a developer, applications engineer, and is currently the Marketing Director for Mentor’s Emulation Division. He holds a BSEE from Clemson University.

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