Formal Verification and Sequential Power Optimization of High Level Synthesis Output
Requires Flash Player.
Overview of sequential formal equivalence checking and its applicability to high level synthesis based flows.
Duration: 30:47
Products: Catapult C Synthesis
View On-demand Web Seminar (Opens in New Window/External URL)
Details
Overview
This session provides an overview of sequential formal equivalence checking and its applicability to high-level synthesis based flows. We will then discuss some of the issues that need to be resolved in using formal equivalence between a high-level model and RTL, and proceed to explain how these are addressed automatically through flows. A typical flow adopted by a user will be shown.
Lastly, we will discuss the need for sequential power optimization to further improve the quality of the RTL, and how the technique fits into a high-level synthesis environment.
What You Will Learn
- How ESL tools help shorten the total design cycle
- The latest advancements in reaching verification coverage
- How to enhance your productivity with state-of-the art ESL technology
Who Should Attend
- Hardware designers
- ESL engineers
- Verification engineers
About the Presenter
Gagan Hasteer
Sr. VP of Engineering, Calypto Design Systems
Gagan co-founded Calypto after making substantial technical contributions to two successful EDA startups. Before co-founding Calypto, Gagan was the Director of Engineering at Innologic Systems, a start-up in the formal verification arena. At Innologic, Gagan successfully managed the development of the company's multi-million dollar flagship product from initial concept to adoption by more than 30 customers before the company's purchase by Synopsys, Inc. Prior to joining Innologic, Gagan was an early member of the Ambit Design Systems engineering team, where he made substantial contributions to the BuildGates synthesis product. Before Ambit, he was a consultant with the Formal Verification group of the MIPS division of SGI. Gagan received an M.S and PhD in Computer Science specializing in Formal Verification of Hardware designs from University of Illinois at Urbana Champaign. He has B.S in Computer Science from Indian Institute of Technology, India.
Related Resources
Multimedia
Power-efficient Design with Catapult C
This webinar presents how design teams can gear up with High-Level Synthesis (HLS) to successfully close on not only timing and area goals, but also on power requirements.…View On-demand Web Seminar
Using the High-Level Synthesis Blue Book
This webinar provides a step-by-step approach for using C++ as a hardware design language.…View On-demand Web Seminar
High-level Synthesis in the TSMC Reference Flow 11
This session steps through the complete Catapult C Synthesis flow as documented in the TSMC Reference Flow 11.…View On-demand Web Seminar
Other Related Resources
High-Level Synthesis in the TSMC Reference Flow 11
White Paper: The result of an ongoing collaboration between TSMC and Mentor Graphics, the TSMC RF11 HLS flow steps a hardware design engineer through the complete Catapult flow from concept to gates, including C to...…View White Paper
A Designer’s Perspective on ESL Methodologies for an OFDM Modem Design
White Paper: This paper presents an ESL methodology from a designer‘s perspective. The design process is explained in context of a high throughput and multi-million gate complexity Orthogonal Frequency-Division...…View White Paper
High-Level Synthesis Walks the Talk: Synthesizing a Complete Graphics Processing Application
White Paper: In this paper, we will describe how a complete graphics processing pipeline was implemented using an HLS methodology. As with most real-life applications, this design consists of a complex mix of control...…View White Paper