Hardware Designs Reuse Using C++ and High Level Synthesis

Overview

The purpose of this webinar is to explain how C++ with High-Level Synthesis (HLS) enhances the reuse methodology at lower risk.

We will explore the C++ language features of classes and templates to create parameterized models. We will then see how HLS synthesizes such models to target ASIC or FPGA together with the required performance and implementation size. HLS technology provides clear separation between functionality (C++) and implementation (RTL Gates). When the decision to reuse or re-implement returns the next time, there is a low risk option of using HLS on a functionality correct model but constrain the synthesis to produce the specified implementation.

As an architect or designer you face this dilemma: should I reuse existing RTL blocks for my next design or design from scratch? The problem is that reuse is often sub-optimal but new design takes time. Meeting specification or the project schedule? Either way there's risk.

What You Will Learn

• How to create parametrizable C/C++ for hardware
• Use template to create flexible C++
• Use Object Oriented techniques for reuse
• Using HLS how to target several hardware architectures
• C++ benefits in hardware design
• How High Level Synthesis enhances reuse by separating functionality and implementation

Who Should View

• System Architects
• System Designers