How to Optimize System Power through Transaction Level Analysis and High-Level Synthesis
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During this webinar, we will describe a technique for adding power characteristics to transaction level models and how transaction level power analysis interacts with high-level synthesis.
Duration: 30:45
Tags: Architecture Design, Clock-Gating, High-Level Synthesis, Low Power, TLM
Products: Catapult C Synthesis, Vista
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Details
Overview
In this discussion you will learn a technique for adding power characteristics to transaction level models and how transaction level power analysis interacts with high-level synthesis.
We will cover the capabilities for defining the power and driving high level synthesis constraints in a top down flow. We will then look at ways to improve the accuracy of the transaction level power models by deriving information from RTL or Gate level implementations including both manually and automatically extracting implementation detail to improve transaction level accuracy.
What You Will Learn
- How to model power at the transaction level
- How power information can be leveraged with high-level synthesis
- The level of accuracy that can be expected in transaction level power models
- How to leverage RTL/gate level implementation information to improve the transaction level power accuracy
About the Presenter
Jon McDonald
Jon McDonald is Sr. Technical Marketing Engineer at Mentor Graphics. He received a BS in Electrical and Computer Engineering from Carnegie Mellon and an MS in Computer Science from Polytechnic University. He has been active in digital design, language based design and architectural modeling for over 15 years. Prior to joining Mentor Graphics Mr. McDonald held senior technical engineering positions with Summit Design, Viewlogic Systems and HHB Systems.
Who Should View
- Project Manager/Project Lead
- Design Architect
- System Engineer
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