Catapult C Synthesis Overview

Related Resources

Multimedia

Formal Verification and Sequential Power Optimization of High Level Synthesis Output

Overview of sequential formal equivalence checking and its applicability to high level synthesis based flows.…View On-demand Web Seminar

Power-efficient Design with Catapult C

This webinar presents how design teams can gear up with High-Level Synthesis (HLS) to successfully close on not only timing and area goals, but also on power requirements.…View On-demand Web Seminar

Using the High-Level Synthesis Blue Book

This webinar provides a step-by-step approach for using C++ as a hardware design language.…View On-demand Web Seminar

Other Related Resources

High-Level Synthesis in the TSMC Reference Flow 11

White Paper: The result of an ongoing collaboration between TSMC and Mentor Graphics, the TSMC RF11 HLS flow steps a hardware design engineer through the complete Catapult flow from concept to gates, including C to...…View White Paper

A Designer’s Perspective on ESL Methodologies for an OFDM Modem Design

White Paper: This paper presents an ESL methodology from a designer‘s perspective. The design process is explained in context of a high throughput and multi-million gate complexity Orthogonal Frequency-Division...…View White Paper

High-Level Synthesis Walks the Talk: Synthesizing a Complete Graphics Processing Application

White Paper: In this paper, we will describe how a complete graphics processing pipeline was implemented using an HLS methodology. As with most real-life applications, this design consists of a complex mix of control...…View White Paper