ESL & HDL Design Solutions
In this session we will review the design complexity challenges and solutions in the ESL & RTL design and synthesis areas that are being offered by Mentor Graphics. Specifically, we will provide an update on Mentor’s ESL and RTL design tools, including: Vista – for Architectural Design of Virtual Platforms Catapult – high level synthesis from C++/SystemC ReqTracer – requirements tracing in a design process Precision – advanced FPGA RTL synthesis Certe – testbench design and creation for OVM Simon Bloch Vice President & General Manager, Design and Synthesis Divsion Mentor Graphics.
Today’s electronic systems embed one or more processors (with software!), bus, cache as well as more and more algorithm mapped in hardware in order to cope with performance requirements.…View On-demand Web Seminar
This session presents an overview of the Veloce emulator and its integration with Vista.…View On-demand Web Seminar
This presentation will look at a number of different architectural choices; exploring how the architecture can be quickly characterized, how decisions can be analyzed and understood.…View On-demand Web Seminar
Other Related Resources
White Paper: Vista Virtual Prototyping provides an early, abstract functional model of the hardware to software engineers even before the hardware design is implemented in RTL. It can run software on embedded processor...…View White Paper
White Paper: The power consumption of devices and the issues around designing for low power are hot topics at this time. This paper looks at the issues from a system-wide perspective and gives guidance on design strategies...…View White Paper