Power-efficient Design with Catapult C
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This webinar presents how design teams can gear up with High-Level Synthesis (HLS) to successfully close on not only timing and area goals, but also on power requirements.
Duration: 24:06
Tags: Catapult C Synthesis, Low Power
Products: Catapult C Synthesis
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Details
Overview
As if it wasn’t difficult enough to deliver area and performance optimized RTL on time, the hardware designer’s job got even more complicated with the increasing pressure to make this RTL power-efficient. This webinar presents how design teams can gear up with High-Level Synthesis (HLS) to successfully close on not only timing and area goals, but also on power requirements.
What You Will Learn
- How ESL tools help shorten the total design cycle
- The latest advancements in reaching verification coverage
- How to enhance your productivity with state-of-the art ESL technology
Who Should Attend
- Hardware designers
- ESL engineers
- Verification engineers
About the Presenter
Thomas Bollaert
Product Marketing Manager, Catapult C Synthesis
Thomas Bollaert is product marketing manager for the Catapult C product line at Mentor Graphics. He has a more than 15 years of experience in EDA, and an extensive background in system-level design and high-level synthesis. More recently, Thomas worked in tight collaboration with Mentor Graphics’ European customers, helping them learn, adopt and deploy high-level synthesis to improve their design practices. He earned his electronic engineering degree from ESIEE Paris where he specialized in hardware architectures for signal processing applications.
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