Sign In
Forgot Password?
Sign In | | Create Account

Saving verification time using TLM modeling



RTL was introduced 15 years ago in order to cope with design complexity that could not be handled with schematic approach.

Can you still match your requirements in a reasonable time with RTL? If yes, no need to change.  Today’s electronic systems embed one or more processors (with software!), bus, cache as well as more and more algorithm mapped in hardware in order to cope with performance requirements. Validating and verifying the complete system is becoming a real challenge both in term of fonctionnality but also performance and power consumption.

ESL methodology together with TLM (transaction level) modeling raise the level of abastraction, like RTL did, in order to cope with today’s challenges

What You Will Learn

  • What is the magic behind TLM modeling (in fact there is no!) to make it faster than RTL
  • What are the different levels of TLM modeling
  • Why TLM modeling is simple

About the Presenter

Presenter Image Yves Pellerin

As European Product Specialist, Yves Pellerin is working with major system and electronic companies for the development of Electronic System Level (ESL) methodologies. Yves expertise lies in electronic design automation as well as ASIC/FPGA design. He has joined Mentor Graphics 12 years ago working in the field on subjects such as emulation, verification, IP and high level synthesis.

Prior Mentor Yves worked for 7 years as consultant for various electronic companies such as Alcatel, MBDA, Thales providing expertise for leading edge Asic designs. Yves holds a master in electronic from the University of Liverpool.

Who Should View

  • Electronic system architects (SoC, boards with processor)
  • Verification managers and users
  • Board, ASIC and FPGA designers

This web seminar is part of our Tuesday Tech Talks.
Learn More

Related Resources


ESL Simulation with Veloce Hardware Emulation

This session presents an overview of the Veloce emulator and its integration with Vista.…View On-demand Web Seminar

ESL & HDL Design Solutions

In this session we will review the design complexity challenges and solutions in the ESL & RTL design and synthesis areas that are being offered by Mentor Graphics. Specifically, we will provide an...…View Technology Overview

SoC Multi-core Architectural Exploration Using Vista

This presentation will look at a number of different architectural choices; exploring how the architecture can be quickly characterized, how decisions can be analyzed and understood.…View On-demand Web Seminar

Other Related Resources

Introduction to Vista

Training Course: The Introduction to Vista course will get you started with ESL design without any knowledge of ESL modeling or tools. This course shows you how to model, simulate, and debug an entire ESL system from scratch...…View Training course

Using a Virtual Prototype: A Sample

Download:  These example and application note provide information and background for using a sample virtual prototype (VP) created using the Mentor Vista product. You can run software on this VP using the Sourcery...…View Download

Vista Virtual Prototyping

White Paper: Vista Virtual Prototyping provides an early, abstract functional model of the hardware to software engineers even before the hardware design is implemented in RTL. It can run software on embedded processor...…View White Paper

Online Chat