Saving verification time using TLM modeling
On-demand Web Seminar
RTL was introduced 15 years ago in order to cope with design complexity that could not be handled with schematic approach.
Can you still match your requirements in a reasonable time with RTL? If yes, no need to change. Today’s electronic systems embed one or more processors (with software!), bus, cache as well as more and more algorithm mapped in hardware in order to cope with performance requirements. Validating and verifying the complete system is becoming a real challenge both in term of fonctionnality but also performance and power consumption.
ESL methodology together with TLM (transaction level) modeling raise the level of abastraction, like RTL did, in order to cope with today’s challenges
What You Will Learn
- What is the magic behind TLM modeling (in fact there is no!) to make it faster than RTL
- What are the different levels of TLM modeling
- Why TLM modeling is simple
About the Presenter
As European Product Specialist, Yves Pellerin is working with major system and electronic companies for the development of Electronic System Level (ESL) methodologies. Yves expertise lies in electronic design automation as well as ASIC/FPGA design. He has joined Mentor Graphics 12 years ago working in the field on subjects such as emulation, verification, IP and high level synthesis.
Prior Mentor Yves worked for 7 years as consultant for various electronic companies such as Alcatel, MBDA, Thales providing expertise for leading edge Asic designs. Yves holds a master in electronic from the University of Liverpool.
Who Should View
- Electronic system architects (SoC, boards with processor)
- Verification managers and users
- Board, ASIC and FPGA designers
This web seminar is part of our Tuesday Tech Talks.
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