Industry Articles

December 2011

Energy Vs. Power: Energy, Power Optimization Is A System-Level Challenge Dec 1, 2011

November 2011

System Performance Analysis and Software Optimization Using a TLM Virtual Platform Nov 22, 2011

April 2011

Cooley Deepchip: Second user confirms CatC does SystemC, control, and prototyping Apr 14, 2011

Cooley Deepchip: Oops! Catapult C tool and 10 readers catch Bluebook quiz mistake Apr 6, 2011

March 2011

Cooley Deepchip: Brett's wrong! User eval confirms Mentor CatapultC does SystemC Mar 25, 2011

Cooley Deepchip: Mentor Bluebook contest has 2 winners out of 1,144 participants Mar 25, 2011

High level synthesis comes of age Mar 17, 2011

February 2011

Seize the Opportunity to Lower Power at the ESL Feb 21, 2011

Experts At The Table: Pain, Abstractions and ESL Feb 4, 2011

January 2011

The DeepChip Top 15 User-Written EDA Technical Letters of 2010 Jan 21, 2011

The DeepChip Top 10 EDA Trip Report and Survey Stories of 2010 Jan 20, 2011

December 2010

The war is over: C++ and SystemC coexist in a single flow Dec 15, 2010

FedEx, McDonald's, and the Mentor C-synthesis Blue Book contest Dec 13, 2010

October 2010

Cooley Deepchip: Mentor CatapultC user on control logic synthesis and AC Channels Oct 26, 2010

Book Review: High-Level Synthesis Blue Book by Michael Fingeroff Oct 15, 2010

September 2010

High Level Synthesis Exposed Sep 21, 2010

Fundamentals of High Level Synthesis - Part 3 Sep 7, 2010

Cooley Deepchip: Users on Mentor Catapult C and Vista at DAC Sep 2, 2010

August 2010

Fundamentals of High Level Synthesis - Part 2 Aug 30, 2010

Fundamentals of High Level Synthesis - Part 1 Aug 23, 2010

July 2010

Give the people what they want: HLS for RTL verification Jul 21, 2010

June 2010

Modern Maturity - Is HLS Ready for AARP? Jun 22, 2010

Implementing Video Analytics on FPGA Using High-Level Synthesis Jun 8, 2010

April 2010

EDA technologies to watch out for at DAC 2010 Apr 29, 2010

Clearing the Hurdles of HLS Adoption Apr 13, 2010

Full-Chip High-Level Synthesis Tool Adds SystemC Support Apr 8, 2010

March 2010

A Look at ESL Mar 11, 2010

February 2010

Power-Optimization Solution Serves Ubiquitous RTL Designer vs Take the High Road to Power-Optimized RTL Feb 8, 2010

January 2010

Bridging ESL and High-Level Synthesis Jan 27, 2010

Mentor adds SystemC support to Catapult C Jan 26, 2010

Mentor embraces SystemC in their Catapult high-level synthesis solution Jan 25, 2010

Combining Power And Synthesis Jan 14, 2010

IC Design Goes Green Jan 1, 2010

December 2009

SystemC and Transaction-Level Modeling (TLM) by Clive Maxfield Dec 21, 2009

ESL Tools Take Center Stage As Designers Move Up Dec 1, 2009

November 2009

Cooley Deepchip: One user's 5 week eval of CatapultC synth vs. hand coded RTL Nov 19, 2009

October 2009

Mentor upgrades Catapult-C to deal with control logic and power management, EDN Oct 7, 2009

September 2009

C synthesis gains momentum, says Mentor Graphics Sep 24, 2009

August 2009

Not For Software Engineers Aug 18, 2009

More Designers Using C Synthesis by End of 2009 Aug 6, 2009

July 2009

How to Future-proof a Hardware Designer Jul 31, 2009

System-Level Design Provides Maximum Control Over Power Jul 28, 2009

SCDsource’s ten hot technologies to see at DAC Jul 24, 2009

Cooley Gadfly: My Cheesy Must See List at DAC Jul 24, 2009

Cooley Gadfly: I Sense A Tremor In The Force Jul 14, 2009

IC Design Tool Unifies C++ Methods for Algorithms and Logic, Electronic Products Jul 2, 2009

ESL...is it What You Want or What You Need? Jul 2, 2009

June 2009

Mentor Catapult C synthesizes Control and Power Management, SCDSource Jun 30, 2009

Catapult C Support control Logic to Enable Full-chip High-level Synthesis, GABEonEDA Jun 30, 2009

Next Step Full-chip Synthesis Jun 30, 2009

Mentor Catapult C synthesizes control and power management Jun 30, 2009

Mentor adds support for control logic to Catapult C, EETimes Jun 29, 2009

Digital functions synthesizable from C++ thanks to Catapult, claims Mentor, Electronics Weekly Jun 29, 2009

Mentor extends Catapult C capabilities to support control-logic, Computer Business Review Jun 29, 2009

May 2009

Cooley Deepchip: Mentor tells Synfora get CatC facts straight May 8, 2009

April 2009

Is ESL Formal Verification an Oxymoron? Apr 29, 2009

Cooley Deepchip: A second US-based C synthesis design reports in Apr 22, 2009

March 2009

Why Bother With ESL? Mar 26, 2009

Cooley DeepChip: A Hesitant RTL Designer Tries Out CatapultC Design Mar 6, 2009

Design Space Exploration for high performance signal processing hardware using ESL design methodologies (featuring Catapult C Synthesis) Mar 2, 2009

February 2009

How High-Level Synthesis Can Raise the Efficiency of Design Reuse Feb 23, 2009

ESL Languages: Which One Is Right For Your Needs? Feb 19, 2009

Cooley DeepChip: What are the 2 biggest reasons to use High Level Synthesis? Feb 5, 2009

January 2009

ESL: The Power Savior? Jan 23, 2009

Keeping the "E" in ESL Jan 23, 2009

December 2008

Cooley DeepChip: Using Calypto SLEC in a Catapult C design Flow Dec 18, 2008

Cooley DeepChip: Power Opto and Linting in CatapultC and Spyglass Dec 18, 2008

Mentor Graphics Receives 2008 Corporate Award from IEEE Standards Association Dec 8, 2008

High-Performance Video Hardware in "No Time" Dec 1, 2008

November 2008

Konica Minolta Designs FPGAs Using Behavioral Synthesis Nov 26, 2008

Cooley DeepChip: The first US-based C/C++ chip design I’ve seen Nov 20, 2008

October 2008

Cooley DeepChip: George is Wrong; SystemC/C++ Tools Play Nicely With Each Other Oct 29, 2008

The Promise of TLM 2.0 - Exploring New Horizons Oct 1, 2008

September 2008

Redefining Design with ESL Sep 30, 2008

Digging into TLM Sep 19, 2008

Prevailing Winds in ESL Sep 18, 2008

Cooley DeepChip: Catapult versus the Competition: DAC Trip Report 2008 Sep 18, 2008

Cross-Talking with TLM 2.0 Sep 16, 2008

Requirements Management is Essential for Today's Complex Electronics Systems Sep 1, 2008

August 2008

Electronic-system-level design: Is there fire beneath the smoke? Aug 21, 2008

July 2008

How high-level modeling speeds low-power design Jul 29, 2008

Modeling cost, availability ups ESL return on investment Jul 15, 2008

Mentor outlines ESL design and verification strategy: SCD Source Interviews Glenn Perry Jul 1, 2008

June 2008

Cutting-Edge Application Demands Engineering Agility Jun 15, 2008

STMicroelectronics Announces Certified Design Flow to Accelerate Creation of Next-Generation Silicon Jun 9, 2008

May 2008

Cooley DeepChip: Troublemaker’s Panel May 8, 2008

FPGA Design Requires Low-power Techniques May 6, 2008

January 2008

System-level Validation Increases Design Productivity and Saves Errors Adobe Acrobat Document Jan 1, 2008

September 2007

Top-down DSP design for FPGAs Sep 5, 2007

New design methodologies offer easier path to custom DSP hardware Sep 3, 2007

May 2007

Sequence and Mentor Graphics Collaborate on ESL Power Exploration Flow May 24, 2007

SPIRIT's the Medium for Success for New FPGA Design May 1, 2007

March 2007

Use ESL Synthesis Techniques to Replace Dedicated DSPs with FPGAs Mar 1, 2007

February 2007

Mentor, MathStar partner on FPOA design tools Feb 27, 2007

December 2006

Power Exploration in High-Level Synthesis Dec 19, 2006

Good or No Good? An Insider Look At What Works For ESL Dec 15, 2006

Focusing on Primary ESL Design Solutions Dec 13, 2006

October 2006

How to use Arbitrary Bit-widths in C++/C-based Algorithm Designs Oct 11, 2006

August 2006

Synthesis tool cuts C-based design effort in half Aug 4, 2006

June 2006

EDA Census: Catapult C Jun 23, 2006

C synthesis tool features larger capacity Jun 13, 2006

Catapult Levels Up: Mentor Attacks ESL Subsystem Design Jun 13, 2006

Mentor Unveils High-Level Synthesis Tool Jun 12, 2006

Tool catapults to subsystem design Jun 12, 2006

Max's Chips and Dips: Mentor Launch Catapult BL and SL Jun 1, 2006

May 2006

Survey Shines Light on the State of ESL Design May 8, 2006

April 2006

Need to accelerate the creation of technology-independent DSP hardware? Apr 18, 2006

February 2006

Industry survey: What is it with ESL? Feb 3, 2006