A Scalable Approach for TLM Across SystemC and SystemVerilog
White Paper
ABSTRACT
There are a number of compelling reasons that SystemC and SystemVerilog should co-exist in advanced verification environments. Hence, many attempts have been made to mix the two languages. The paper addresses the limitations of these current approaches, specifically in terms of scalability for multiple transactions types and dynamic allocation of data to be transferred across the language boundary. A general and scalable method for mixing SystemC and SystemVerilog data transactions and models will be presented, accompanied by working example code taken from real-life projects.
Related Resources
Vista Virtual Prototyping
White PaperVista Virtual Prototyping
Vista Virtual Prototyping provides an early, abstract functional model of the hardware to software engineers even before the hardware design is implemented in RTL. It can run software on embedded processor...
TAGS: Architecture Design, Architecture Validation, TLM, Vista
Embedded System Power Consumption: A Software or Hardware Issue?
The power consumption of devices and the issues around designing for low power are hot topics at this time. This paper looks at the issues from a system-wide perspective and gives guidance on design strategies...
Saving verification time using TLM modeling
On-demand Web Seminar 23:10Saving verification time using TLM modeling
Today’s electronic systems embed one or more processors (with software!), bus, cache as well as more and more algorithm mapped in hardware in order to cope with performance requirements.