Advanced Clock Gating Techniques in Catapult C Synthesis
White Paper
ABSTRACT
This whitepaper discusses one of the most important power optimization techniques used in Catapult C Synthesis – advanced clock gating optimization and analysis. Electronic System Level (ESL) design methodologies enable power consumption optimization opportunities unreachable for traditional RTL design methods. Learn how Catapult C Synthesis can help you deliver designs with minimum power dissipation using its several power optimization methods and power-aware architecture exploration capabilities.
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