High-Level Synthesis in the TSMC Reference Flow 11
White Paper
ABSTRACT
The result of an ongoing collaboration between TSMC and Mentor Graphics, the TSMC RF11 HLS flow steps a hardware design engineer through the complete Catapult flow from concept to gates, including C to RTL verification, while targeting TSMC technology. Deliverables—such as the TSMC 65 nm and 40 nm low-power HLS libraries and the TSMC memory compiler integration—provide the necessary foundation to start using Catapult C on the next TSMC design.
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