Stepwise Refinement and Reuse: The Key to ESL
White Paper
ABSTRACT
In this paper we will illustrate the essential elements of a five step refinement flow. The first four steps in the flow have been realized in TSMC’s Reference Flow 11 and work is ongoing for reference flow 12. We will briefly show results from reference flow 11 and discuss the work underway for reference flow 12.
A stepwise refinement and reuse flow is necessary to realize the complete benefits of ESL. It preserves each subsequent modeling investment through the transformation and verification of transaction-level models from their initial highly abstracted representation to fully verified RTL. It utilizes transaction-level models as reference models during RTL verification and reuses the initial TLM platform as a “system level testbench” for downstream implementations.
Related Resources
Vista Virtual Prototyping
White PaperVista Virtual Prototyping
Vista Virtual Prototyping provides an early, abstract functional model of the hardware to software engineers even before the hardware design is implemented in RTL. It can run software on embedded processor...
TAGS: Architecture Design, Architecture Validation, TLM, Vista
Embedded System Power Consumption: A Software or...
White PaperEmbedded System Power Consumption: A Software or Hardware Issue?
The power consumption of devices and the issues around designing for low power are hot topics at this time. This paper looks at the issues from a system-wide perspective and gives guidance on design strategies...
Saving verification time using TLM modeling
On-demand Web Seminar 23:10Saving verification time using TLM modeling
Today’s electronic systems embed one or more processors (with software!), bus, cache as well as more and more algorithm mapped in hardware in order to cope with performance requirements.
