Vista Virtual Prototyping
White Paper
ABSTRACT
Vista Virtual Prototyping provides an early, abstract functional model of the hardware to software engineers even before the hardware design is implemented in RTL. It can run software on embedded processor models at speeds par with board support packages, providing sufficiently fast simulation models for OS and application software validation. The Vista Virtual Prototyping solution has two distinctive components: creation of the transaction-level modeling (TLM) platform and usage of the virtual prototype.
Related Resources
Embedded System Power Consumption: A Software or Hardware Issue?
The power consumption of devices and the issues around designing for low power are hot topics at this time. This paper looks at the issues from a system-wide perspective and gives guidance on design strategies...
Saving verification time using TLM modeling
On-demand Web Seminar 23:10Saving verification time using TLM modeling
Today’s electronic systems embed one or more processors (with software!), bus, cache as well as more and more algorithm mapped in hardware in order to cope with performance requirements.
Stepwise Refinement and Reuse: The Key to ESL
White PaperStepwise Refinement and Reuse: The Key to ESL
In this paper we will illustrate the essential elements of a five step refinement flow. The first four steps in the flow have been realized in TSMC’s Reference Flow 11 and work is ongoing for reference...
TAGS: TLM