Technology Overview 01:13:13
9th ESL Symposium Panel Discussion at DAC 2011
Executives from Intel, ARM, Freescale, ST and Mentor will examine the industry-wide move to ESL by highlighting the views and experiences of executives from leading semiconductor, IP and EDA companies.
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High-Level Synthesis in the TSMC Reference Flow 11
The result of an ongoing collaboration between TSMC and Mentor Graphics, the TSMC RF11 HLS flow steps a hardware design engineer through the complete Catapult flow from concept to gates, including C to...
TAGS: C synthesis, Catapult C Synthesis, ESL Verification, High-Level Synthesis, Low Power, OVM, System Verilog, SystemC, TLM, TSMC
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High-Level Synthesis Walks the Talk: Synthesizing a Complete Graphics Processing Application
In this paper, we will describe how a complete graphics processing pipeline was implemented using an HLS methodology. As with most real-life applications, this design consists of a complex mix of control...
TAGS: C synthesis, C++, Catapult C Synthesis, Control-Logic Synthesis, ESL Verification, High-Level Synthesis, Optimization, SystemC, SystemVerilog, Verification
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A Designer’s Perspective on ESL Methodologies for an OFDM Modem Design
This paper presents an ESL methodology from a designer‘s perspective. The design process is explained in context of a high throughput and multi-million gate complexity Orthogonal Frequency-Division...
TAGS: C synthesis, C++, Catapult C Synthesis, Control-Logic Synthesis, High-Level Synthesis, STMicroelectronics, SystemC, User Testimonial
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Stepwise Refinement and Reuse: The Key to ESL
In this paper we will illustrate the essential elements of a five step refinement flow. The first four steps in the flow have been realized in TSMC’s Reference Flow 11 and work is ongoing for reference...
TAGS: Optimization, Simulation, TLM, Verification, Vista
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On-demand Web Seminar 13:08
Virtual Prototyping Using Vista
See Vista Virtual Prototype, a unique solution enabling fast and efficient software debugging and analysis cycles in the context of the target hardware.
TAGS: Vista
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Technology Overview 31:34
ESL & HDL Design Solutions
In this session we will review the design complexity challenges and solutions in the ESL & RTL design and synthesis areas that are being offered by Mentor Graphics. Specifically, we will provide an...
TAGS: Catapult C Synthesis, Certe, Emulation, High-Level Synthesis, ReqTracer, Verification, Vista
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Hardware-Aware Virtual Prototyping
Hardware-aware virtual prototyping is the best way to optimize system performance, power consumption, and cost and enable concurrent HW/SW development. Using a multi-core design, this paper demonstrates...
TAGS: Architecture Design, Architecture Validation, ESL Verification, TLM, Vista
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On-demand Web Seminar 23:16
ESL Verification in the TSMC Reference Flow 11
See how an ESL verification environment is created, validated and debugged, and how ESL verification components are reused by advanced RTL verification environments such as OVM.
TAGS: ESL Verification, Reference Flow, TSMC
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