Alcatel

A new design flow was needed…fast

The Alcatel Space division, one of the world’s leading satellite manufacturers, faced two major problems with its previous design flow for digital signal processing (DSP) ASICs. Given their time-to-market objectives, they couldn’t fully explore the range of viable RTL architectures available. The second hurdle was the discontinuity between the "golden" C++ model and the RTL description, which further complicated the flow due to the potential errors introduced in the manual translation. They wanted their new flow to use their “golden” C++ model to automatically generate the RTL and also needed the ability to quickly explore alternative micro-architectures.

Alcatel evaluates Catapult C Synthesis

Having been familiar with Catapult C Synthsis, the team decided to perform a full evaluation. There were five FPGAs used in the evaluation design to implement the functionality of one ASIC. One of the design blocks performed an incredibly complex algorithm in 8 stages. Initial testing was performed upon three small functional blocks. The first was from the power recovery stage, the second was from the timing recovery stage, and the third was a filter block from the frequency recovery stage.

Catapult C Synthesis allows the design teams to leverage their libraries of existing "golden" C++ models and fully explore the range of viable RTL architectures available.

Optimal designs in less time

In the words of Louis Baguena, the ASIC/FPGA Design Manager at Alcatel Space, "Using our traditional RTL flow, three blocks took approximately nine weeks to design. Once we were up to speed on Catapult C Synthesis, all three blocks were done in three weeks starting from the original un-timed C++ source, representing an impressive 3x improvement. The most surprising outcome, however, was the resulting RTL design was not only equivalent to the hand-coded design but in some cases actually smaller and faster." Alcatel can now use their "golden" C++ models to automatically create high-quality RTL designs. More importantly, Catapult C Synthesis gives them the ability to tradeoff area and performance requirements via micro-architecture exploration, ultimately converging on optimal implementations for all design blocks.