Ericsson

The RTL design bottleneck

The Ericsson Mobile Platforms R&D team in Sweden used a C/C++ reference model to simulate and validate the functionality of their algorithms and to ultimately compare the representations against RTL implementations. However, embedding specific micro-architecture decisions in the RTL for physical implementation means Ericsson often had to keep the first design that met their specifications, even though they knew they could do better. Plus, design reuse was problematic and could only take place at the cost of silicon efficiency.

Catapult C Synthesis is introduced and evaluated

Mentor Graphics introduced Ericsson to the concept of algorithmic C synthesis, now known as Catapult C Synthesis. Catapult C Synthesis allows design teams to easily use the same C/C++ models they had already created for simulation, which was of utmost importance for the team at Ericsson. Three evaluations were performed: the first on a W-CDMA 3G modem algorithm called EPC, and the second on a standard 2D graphics acceleration algorithm called IDCT. The third evaluation was to be performed on a GSM algorithm, but the number of real operations exceeded the capacity of Catapult C Synthesis at the time. Mentor’s close relationship with Ericsson enabled them to utilize the feedback and increase the tool’s capacity for subsequent releases.

An unqualified success

The first evaluation featured datapath and control elements blended together. What took an experienced designer two months with 45,000 gates now took only 2 ½ weeks and a resulting gate count of 30, 827 – a 31% reduction. This, in turn, produced a reduction in area and improvement in power consumption. The second evaluation produced a 20% reduction in gate count and allowed the team to get the block out the door very quickly. The Ericsson facility expanded from the initial seat to ten seats within a year and has another development group also adopting it. It is widely agreed that the Catapult C Synthesis evaluation was very successful.