Hitachi, Ltd.
Success Story
ABSTRACT
The Hitachi, Ltd., Telecommunication & Network Systems Division planned to develop a Forward Error Correction (FEC) system to meet the needs of next generation communication systems. FEC devices correct errors due to imperfect transmission and as such, are very important for the reliability of data transfer over longer distances. Error detection and correction typically works by mixing and detecting the noise under transmission, a process which involves many complicated calculations and where algorithm efficiency directly translates to hardware complexity. In this context, Hitachi’s project was considered to be a very challenging one.
“During the evaluation, we had a tricky corner-case bug that required 20k patterns of simulation data to trigger. While running those patterns took only an hour in the C simulation, and it would have taken almost 960 hours (or 40 days) in RTL simulation. ”
Hitachi, Ltd., Telecommunication and Network Systems Division
When the Hitachi team completed the FEC project, they were confident in Catapult C Synthesis and in their choice to adopt a high-level synthesis tool. Since this first experiment, the team has leveraged the benefits of the Catapult C Synthesis methodology on eight consecutive tape-outs (both ASIC and FPGA), the latest one being a7.9M gate ASIC, 57% of which were synthesized from C with Catapult C Synthesis.
“Initially, we created designs in both the traditional and the Catapult C Synthesis based flows to alleviate the fear involved in changing methodologies. After we proved the results with the Catapult C Synthesis flow were acceptable, especially from an ease of use standpoint for example Catapult can generate various RTL code by single C code, we began moving to a high-level synthesis strategy for complicated algorithmic designs.”
Hitachi, Ltd., Telecommunication and Network Systems Division
Related Resources
Learn more about Catapult C Synthesis
Related Resources
High-Level Synthesis in the TSMC Reference Flow 11The result of an ongoing collaboration between TSMC and Mentor Graphics, the TSMC RF11 HLS flow steps a hardware design engineer through the complete Catapult flow from concept to gates, including C to... TAGS: C synthesis, Catapult C Synthesis, ESL Verification, High-Level Synthesis, Low Power, OVM, System Verilog, SystemC, TLM, TSMC |
A Designer’s Perspective on ESL Methodologies for an OFDM Modem DesignThis paper presents an ESL methodology from a designer‘s perspective. The design process is explained in context of a high throughput and multi-million gate complexity Orthogonal Frequency-Division... TAGS: C synthesis, C++, Catapult C Synthesis, Control-Logic Synthesis, High-Level Synthesis, STMicroelectronics, SystemC, User Testimonial |
High-Level Synthesis Walks the Talk: Synthesizing a Complete Graphics Processing ApplicationIn this paper, we will describe how a complete graphics processing pipeline was implemented using an HLS methodology. As with most real-life applications, this design consists of a complex mix of control... TAGS: C synthesis, C++, Catapult C Synthesis, Control-Logic Synthesis, ESL Verification, High-Level Synthesis, Optimization, SystemC, SystemVerilog, Verification |