Sonics, Inc. Realizes Significant Design Productivity Gains by Modeling at a Higher Level Using Mentor Graphics ESL

 Sonics Inc.® is the premier supplier in the interconnect segment of the Semiconductor Intellectual Property (SIP) market. The company's SMART InterconnectTM solutions and Memory Management products facilitate the rapid development of Systems-on-A-Chip (SoC) for embedded systems markets. By using SMART Interconnect solutions, SoC developers can shift interconnect and intellectual property design and verification from the physical design phase to the architectural exploration phase of the chip development process. This has proven to save significant amounts of time and development costs while lowering project risks in a variety of leading-edge designs in the wireless, digital multimedia, and communications markets. As a result, designers can develop SoCs in a fraction of the time and at a fraction of the cost when compared to architecting.

Modeling at a Higher Level

The push for more functions, higher speed, and lower power requires seamless operation between the processor core(s) and the on-chip interconnect, which control the system, the processors that manipulate or display data, and the rest of the SoC. Since the interconnect lies at the heart of a customer's SoC, Sonics goes to great lengths to carefully design and verify their products. To that end, they provide customers with a whole range of verification data on the interconnect SIP to ensure a smooth integration into the customer's SoC design environment. In today's advanced SoC design environment, that means providing SIP and its supporting battery of tests at both the register transfer level (RTL) and at higher levels of abstractions—specifically SystemC transaction level models (TLM).

Designers of next-generation SoCs are moving to higher levels of abstraction to handle the enormous volume of design detail when creating integrated circuits that contain tens of millions of gates. Working at a higher level of abstraction enables them to quickly examine and compare different architectural approaches, choosing the optimal one to meet power, performance, size and cost goals.

Many designers now use SystemC TLM to create virtual prototypes which model systems at a functional level, link with software to enable quick review of architectural design decisions, and allow the hardware team to repair errors well before committing to a RTL. SystemC TLM abstracts communication and data transfers, leading to faster simulation while preserving functional parameters. TLM allows separating communication, functionality and implementation, thereby enabling incremental model fidelity for timing and power. This modular approach dramatically reduces the time needed to create and refine the models.

The scalable TLM model in SystemC benefits both the hardware and software development. Not only can the software team validate their software much earlier in the design cycle, but it supports much faster verification times – 100x or more – making it a viable solution. In essence, the TLM model in SystemC is independent of the hardware mechanics, allowing the hardware team to continually refine the design without having to make painstaking updates to a detailed RTL virtual prototype.

Creating a Robust SystemC Transaction-Level Model

For all of its system validation and exploration benefits, SystemC TLM remains a fairly new methodology. Even though it involves far less effort than RTL creation, transaction-level modeling is a significant design step. Any errors captured at TLM will cascade throughout the design phase, leading to substantial design and verification challenges later on.

Sonics decided to offer pre-verified transaction-level models of SMART Interconnect solutions that would significantly reduce users' system-level verification challenges when architecting SoCs with the TLM methodology. However, the challenge of debugging the SystemC TLM models quickly became apparent. The creation of SystemC models is a relatively new discipline for designers, compared to RTL model creation which is a well-known, established process with a plentitude of tools and test suites to support that process. Part of the challenge stems from the fact that SystemC derives from the programming language C++ with the addition of language constructs to describe hardware functionality and timing. As such, SystemC has one foot in the software world and the other in the hardware realm, making it somewhat difficult for hardware designers to understand and use with ease. Moreover, the tools for working in SystemC are not as extensive and robust as those for more mature environments such as RTL.

To debug the SystemC models and Systems that they were generating, Sonics turned to Mentor Graphics for help. Specifically, they adopted Mentor Graphics' Vista™, a SystemC IDE and debug toolset. Vista is the industry's most advanced SystemC debug toolset, providing powerful hardware and C/C++ oriented views and debugging mechanisms. Using Vista, Sonics engineers were able to reduce debug cycles by 20%, effectively reducing time to market for transaction-level models of their SMART Interconnect solutions. Vista supports the TLM methodology without instrumentation while providing designers with unique debug functionality and viewers that make the debug process easy to understand. Vista allows designers to intuitively visualize and trace C/C++ hierarchy and execution in a HW context over time under any SystemC environment and mixed-language simulation kernels including OSCI, Mentor's Questa or Cadence Incisive.

Vista's IDE setting makes it intuitive to learn and use, enabling Sonics' designers to quickly become proficient in the environment. Unlike Sonics' previous non-graphical debuggers, which required substantial knowledge and expertise to use effectively, many more Sonics engineers quickly ramped on Vista. For example, the Vista browser helps check that the system has been correctly elaborated. It also allows instance replication because the viewer understands hierarchy.

Now with Vista, instead of one or two "debug experts", any of the designers can easily work more independently when encountering a problem. Unlike competing solutions, Vista is compatible with SystemC, eliminating the need to switch the entire environment when debugging, and further streamlining the debug effort. The transaction viewer helps system-level debugging because the user is able to see why something hangs at the last transaction and what executed before the failed one. The transaction viewer lists a timeline of all the function calls allowing tracing the arguments more explicitly than the non-graphical debugger.

The graphical display environment has the additional benefit of making it easy to debug any integration issues when a customer incorporates the SystemC model into their target SoC design. Now Sonics designers can help customers quickly resolve issues, such as port incompatibilities, minimizing the frustrations that often occur when incorporating 3rd party SIP.

Thanks in part to a fully debugged SystemC transaction-level model, Sonics' pre-verified SystemC platform promotes design predictability and minimizes the product development risk, leading to faster design cycles and enabling the software development teams to take advantages of hardware configurations earlier in the development cycle. With these enhancements to SoC designs, Sonics is improved cost and performance benefits for multi-core SoC development.

Looking to the Future

As Sonics moves to its next-generation of interconnect SIP, they anticipate having to accommodate the ever expanding demands of high end consumer and wireless SoC design. Next-generation switch fabrics will increase in complexity to support multimedia applications and new communications standards. That means higher bandwidths, larger feature sets and the ability dynamically vary speeds to achieve lower power.

All these will require more simulation capability at the SystemC TLM level. Besides using Vista to help them debug ever more complex interconnect SIP, Sonics is also working on using Vista to perform co-simulation between the reference model in SystemC and the resultant RTL models. With customers demanding more cycle-accurate models, co-simulation is key in supporting this advanced level of modeling. With that said, the co-simulation effort is much more complicated to put in place, however, Sonics is working with Mentor to make this a viable reality.

To that end, Mentor Graphics and Sonics are ensuring interoperability between Mentor's electronic system level (ESL) design tools and the SystemC versions of Sonics SMART Interconnect solutions. Mentor Graphics' ESL tools, including Vista™ and Visual Elite™, an ESL/RTL system integration tool, support Sonics' abstracted designs, providing a continuous flow to address interconnect challenges in leading-edge SoCs.

Providing these capabilities at different levels of abstraction simplifies and amplifies the ability to quickly re-use, substitute, or adding intellectual property (IP) for the next generation product, or even porting to the next process technology node.

"Success in the ESL design space requires more than just point tools; it requires integration among best-in-class tools and IP in order to deliver maximum value for customers," said Glenn Perry, Mentor Graphics general manager of ESL. "We are pleased to cooperate with Sonics and their engineering team in order to deliver more efficient tools that are tightly aligned with our mutual customers' requirements."