Complex design challenges characterized by shrinking geometry, functionality within both the hardware and software domains, and strict requirements for performance and power efficiency driven by the designated application, are changing how systems are being designed.
In the consumer markets, user’s experience is a key for product success. It is determined by the performance of the combined hardware and software application. To achieve an optimal architecture and allow design scalability, design engineers must maintain visibility over the power and performance requirements ahead of production when the greatest impact on design implementation is still possible.
Challenges & Features
- Define optimal macro and micro Architecture
- Perform analysis for implementation architectural tradeoffs
- Understand the impact of key design attributes on design timing and performance goals
- Allows for hardware vs. software implementation tradeoffs
- Analyze performance while running software
Features & Benefits
- Set of configurable TLM 2.0-based architecture blocks
- Intuitive graphical platform assembly tool
- Tracing of data packets, model states and design attributes
- Advanced analysis and visualization
- Hardware / software tradeoff analysis
- Early assessment of timing and power
Architecture design is the task carried by the system architects and SoC designers who need to architect, integrate and optimize complex systems meeting power and performance requirements.
During the platform definition process, macro-architecture and micro-architecture decisions need to be made such as HW/SW tradeoffs, processors selection, interconnect and memory hierarchies, fabric infrastructures, and caching strategies.
When designing complex interconnect fabrics (such as storage and networking), architecture exploration is usually done ahead of the functional design phase by using statistical non-functional models and traffic generators that simulate various data distributions and loads. Alternately, in SoC and embedded applications, performance can be explored along with functional validation and software execution. It is critical to be able to balance power and performance in conjunction with hardware and software functionality, and then trade hardware vs. software implementations in a methodical and predictable way.
Architecture exploration may require numerous iterations and therefore is not practical using a RTL platform. Arguably, most RTL implementation details are redundant at the design architectural exploration stage, but there is a need to have some visibility of the timing and power characteristics for a meaningful assessment and analysis to occur.
A transaction level reference platform is ideal to serve such requirements and enables an efficient exploration process. It allows fast exploration for quantifying the performance and power before actual implementation. It facilitates quick simulation and analysis iterations around various architectural options as well as software execution.
The TLM platform is an ideal exploration vehicle for system architects as it provides a natural path to the hardware and software downstream design flows. Given the time and money at stake, the transaction level platform delivers risk reduction and a more predictive design flow that are now vital for companies that demand reliability, cost effectiveness and design scalability.