Sign In
Forgot Password?
Sign In | | Create Account

Vista Flow

Create TLM models, debug, optimize and more

The Vista™ Flow consists of the steps typically used by SoC Architects, hardware engineers and software engineers to create TLM Models, assemble and configure the system, simulate, verify and debug, analyze and optimize performance and power and integrate with software.


  • Architecture design and exploration
  • Allow hardware / software tradeoffs analysis
  • Early assessment of performance and power
  • Virtual platform for software integration and validation
  • Reference modeling for RTL verification
  • Minimizes risks and maximizes quality of results

Create TLM Models

Vista Model Builder, a sub-set of the Vista Architect solution, facilitates TLM model creation, allowing users to efficiently create complex models using intuitive mechanisms and a set of pre-defined modeling base classes. Vista Model Builder is augmented with a new scalable modeling methodology, based on TLM 2.0, where communication, functionality, and timing/power attributes are independently modeled. This important modeling practice allows a single functional model to be maintained throughout the design cycle at various implementation phases and through alternative design options.

Vista Model Builder automates the functionality modeling with a set of TLM classes and convenience layer for more efficient and guided behavioral modeling. A TLM code skeleton is automatically derived from a set of ports, registers and memory declarations generating compact SystemC source code compliant with TLM 2.0, so users can completely model the internal behavior.

Timing and power can be specified in a top-down manner through a set of powerful policies. The policies are used to intuitively model the timing of a desired micro-architecture including latencies, pipelining and wait states declarations. This approach allows users to quickly explore various complex micro-architecture alternatives in the system context with minimal coding effort while keeping the code representing the functionality intact.

Vista Model Builder Timing Policies
Vista Generic Library View

Vista TLM Models

Vista Architect offers a set of fast generic models for initial platform assembly and early validation. All models are TLM 2.0 compliant and can be used as building blocks for assembling any target platform.

In addition, users can use third party TLM 2.0 compliant processor and peripheral models that have been integrated and validated with Vista Architect.

The list of models includes:

  • CPU [With SW Thread]
  • BUS [AHB, AXI]
  • MEM
  • Cache
  • DMA Controller
  • Interrupt Controller
  • Timer

Verify and Debug the System

Vista Architect offers the industry's most advanced SystemC debug toolset (Vista Debug) designed to validate and debug SystemC TLM platforms. At the architecture level, verification is focused on validating the correct interaction among various IPs and appropriate flow of data.

Vista Architect presents innovative debugging and tracing concept that focuses on high-level system debug and data flow analysis. It helps users understand how data is processed and passed through the system and its resources, understand the sequence of events, flow control and process scheduling.

Unique debugging mechanisms tailored for TLM 2.0 and SystemC/C/C++ modeling allow users to trace transactions, sequence of events and process execution within a familiar hardware debugging platform. Users can view design hierarchies as well as class hierarchies and understand how C/C++ data objects and functions are assigned and executed over time or even within delta cycles. All TLM level debug and analysis are supported without any source code instrumentation and links naturally with any existing SystemC Design flow.

Transaction Level Viewing in the Waveform
Debugging Vista Processes
Vista Transaction Sequence Viewer
Vista Block Diagram Editor

Assemble and Configure the System

During the architecture design phase, models can be intuitively instantiated and assembled into various architecture configurations, interconnect layering and memory hierarchies. Vista powerful block diagram editor provides an intuitive graphical platform assembly, editing and visualization.

Integrate with Software

Users can test and debug the hardware driven by software or produce a virtual platform to run firmware, operating systems or hardware dependent software applications.

Vista Integrated Software Debuggers (GDB, ARM RVDE, MENTOR EDGE)
Vista Simulation Console

Powerful Analysis Toolset

Vista Architect offers a powerful analysis and reporting toolset that allows users to intuitively analyze different performance and power metrics by looking at load peaks, average latencies, throughput and utilization on any port, bus or sub-system without any manual instrumentation.

With Vista Architect users can rapidly prototype systems by assembling key hardware blocks and analyzing the system power consumption and performance under different scenarios and traffic loads. The scalable modeling approach supported in Vista Architect enables design teams to manage timing and power budgets from concept down to the desired implementation. This approach ensures that the silicon area is optimized and that the system is able to carry the data capacities for a given application. It also insures that the system architecture is scalable to support future derivations of the product.

Exercise Various Scenarios

Complex data packets can be easily created and tagged with an “ID”, and then traced and analyzed as they propagate through the system. This unique capability allows users to clearly understand the flow of data through the system and the impact of various loading scenarios.

Users can exercise statistical and randomized data traffic or run SW-driven traffic, testing realistic use case scenarios. This allows for detailed analysis of the hardware and software domains tradeoffs and optimizing the hardware / software boundaries in the architecture.

With Vista Architect users can apply the scalable TLM modeling approach for improved modeling and simulation efficiencies. They can dynamically switch from a pure loosely-timed (“LT”) simulation to approximately-timed (“AT”) simulation.

Quickly Change the Micro-architecture

The unique layered approach for modeling timing enables users to quickly change the timing policies for each micro-architecture model and test various configurations and pipeline strategies while keeping the functionality intact. Users can refine the timing and power accuracy based on the target bus protocol from high-level approximation down to precise timing in a matter of minutes.

Online Chat