Power analysis limitations at the higher level cause most people to handle power requirements post-place-and-route, or minimally, post-synthesis.
The degrees of design freedom gained at the post-synthesis stage are quite modest compared with optimizing power in the context of the system early in the design phase. Specifically, hardware/software partitioning, bus implementation, architectural choices for memory control and management, and hardware acceleration all have enormous potential for impacting power improvement relative to the backend gains.
A new generation of tools
A new generation of tools from Mentor delivers modeling fidelity and simulation performance at the early design exploration stage. These tools rely on the progress made in the electronic system level (ESL) space to map the performance and power information from gate level block representations into the transaction-level modeling (TLM) domain, which substantially improves simulation performance, while maintaining a high fidelity of modeling accuracy.
Mapping of accurate performance and power information is possible due to the extreme dependency on block-based reuse in modern design. Synthesizable RTL exists for a large portion of any new design at inception, and the balance of content can often be synthesized directly from TLM representations using high-level synthesis. Performance and power information can be extracted from these block-level representations and mapped into the TLM domain.
How It Works
These tools enable the creation of a high-level timing and power model with minimal modeling resources required. These high-level models facilitate two key activities.
The first is building a parameterizable model of the architecture that can be used for architectural analysis and optimization for both the hardware and software. The platform can provide the simulation performance, timing, and power accuracy to make intelligent architectural decisions based on the target application, processing requirements of user specific data streams, and software interaction with the hardware.
Second, the technology exists to extract detailed timing and power models from the implementation at this early stage in the design cycle. The models must remain truly abstract to maintain the level of performance required to be effective in architectural analysis. These extracted models can be cycle-accurate at the transaction level. The extracted models provide a path to verify that throughout the entire design cycle, the implementation satisfies the requirements of the system quantified in the first stage of architectural analysis.