Vista
A Complete TLM 2.0-based Solution
Vista™ is a complete TLM 2.0-based solution for architecture design, analysis, verification and virtual prototyping enabling system architects and SoC designers to make viable architecture decisions and enabling hardware and software engineers validate their hardware and software.
This is accomplished by prototyping, debugging and analyzing complex systems early in the design cycle, even before RTL to achieve predictable and productive design process, and first pass success.
9th ESL Symposium Panel Discussion at DAC 2011
Technology Overview: Executives from Intel, ARM, Freescale, ST and Mentor will examine the industry-wide move to ESL by highlighting the views and experiences of executives from leading semiconductor, IP and EDA companies. View Technology Overview
Vista Use Models
Architecture Design Exploration
Architecture design is carried by system architects and SoC designers, who architect the system topology. They use an iterative exploration process by simulating, analyzing and optimizing the architecture to meet power and performance objectives. Architecture Design Exploration
Architecture Validation
Architecture validation focuses on verifying and debugging at the transaction level (TLM) abstraction. System designers and verification engineers need to simulate and validate that the system functionality and the interaction among design blocks is correct, and debug any errors found. Architecture Validation
Virtual Prototyping
Virtual prototyping is used to create a virtual platform of the hardware to be able to run, debug and optimize firmware, operating systems and software applications against it. Virtual Prototyping
Vista Flow
The Vista Flow consists of the steps typically used by SoC Architects, hardware engineers and software engineers to create TLM Models, assemble and configure the system, simulate, verify and debug, analyze and optimize performance and power and integrate with software.
Design Solutions
Transaction Level Modeling
Transaction Level Modeling (TLM) is one a key ESL methodology that allows TLM model creation. It includes modeling the functionality, the timing and power, and the communication interfaces at a higher level of abstraction. Transaction Level Modeling (TLM)
Low Power
Vista ESL breakthrough solution lets you tackle the power requirements early at the architecture level and allows designers to optimize and meet power budget requirements before committing the architecture to implementation. Low Power Solutions
Background
ESL Design, Verification & Virtual Prototyping
System developers face significant challenges to integrate the system complex hardware with software running on multi-core processors and to comprehend the combined impact of the architecture on the system power, performance and functionality. The most common approach used in the past was to develop the system hardware and software components in isolation while integrating and testing these at the end of the design cycle. As a result, product development time was longer and the opportunity to make architectural modifications is lost.
Creating transaction level platforms early in the design cycle ensures that the system can implement the desired functionality while handling its load and data traffic capacities. Furthermore, it allows for validating the software against the hardware even before RTL is implemented and tuning the multi-core hardware architecture and embedded software to meet performance and low power requirements.
Key Questions (At the Architectural Level)
- Can the architecture deliver the necessary functionality and meet user expectations?
- Can the system meet performance and power consumption goals?
- Can the system specification be effectively implemented?
- Can software run correctly and efficiently on the target architecture?
Before and After: Optimizing Performance