Transaction Level Modeling
Standard Communication Layer Based on TLM 2.0
The transaction level modeling process and methodology sets the foundation for the entire design flow and substantially impacts efficiency and sustainability. Transaction Level Modeling (TLM) is a key ESL concept that allows modeling communication at a higher level by abstracting cycle by cycle hardware signal changes to abstract operations.
TLM 2.0 Key Facts
- Standard communication layer based on OSCI TLM 2.0 standard
- Uses C/C++ and SystemC and is being extended to SystemVerilog
- Suitable for both hardware and software modeling
- Used for validation and analysis
- Defines both data and control type communication protocols
- Contains standard payload definition
- Provides memory and debug interfaces
Features and Benefits
- Innovative TLM 2.0 modeling approach
- Layered modeling methodology
- Separation of communication, function and timing/power layers
- Enables incremental model refinement for timing and power
- Compatible with hardware verification and software execution requirements
- Consistent from system level to implementation
- Automates TLM 2.0 model generation
- Reduces modeling effort
- Separates functionality from communication
- Classes for behavioral modeling
- Timing/Power policies
- Eases the exploration of various micro-architectures
At the TLM, users can use function calls to execute read or write operations of a single word, or a complete data packet. TLM also results in modeling the functionality of the system using a higher level description and more abstract data objects.
TLM 2.0 is the TLM OSCI standard and allows for model interoperability throughout the design community. TLM 2.0 sets the infrastructure for ESL design across the industry and drives reuse and interoperability among IP providers, semiconductor companies, and system companies. TLM 2.0 is also essential in driving the ESL methodology for overall improvement of design creation and verification efficiency. TLM 2.0 defines two key modeling mechanisms, loosely-timed (“LT”) and approximately -timed (“AT”) that can serve various modeling needs and use cases. It defines how models exchange data at different layers and defines the data payload.
Scalable Modeling Methodology
Transaction level modeling (TLM) provides an abstract design methodology that supports modeling, validation, analysis and implementation. Mentor Graphics is offering a TLM 2.0 Scalable Modeling Methodology, based on a layered approach that separates communication, functionality and power/timing. The layered approach allows a model to maintain a single functional description throughout the entire ESL design cycle all the way to implementation.
While the functional un-timed layer defines the model behavior for “what” it does, the timing/power layer reflects, “how” the function is implemented. The “timing” layer essentially captures the timing associated with a given function micro-architecture implementation reflecting the latency of computation, the pipelining across ports or the response time (such as number of wait states).
During the design process, timing and power accuracy evolve with the model refinement process from an abstract un-timed view into a detailed implementation view of the target micro-architecture, all of which are represented within a single model.
Using this layered approach also allows using the same model in a switchable mode, alternating between fast un-timed software execution mode (in “LT” mode) or detailed simulation mode for hardware verification and performance/power analysis (in “AT” timed mode).