Virtual Prototyping
Test Your Software Against Early Hardware Model
One of the primary purposes of building a transaction level platform of the hardware implementation of the system is to create a Virtual Platform that can be used for firmware testing, operating system integration and hardware-dependent application development.
Using TLM and SystemC/C/C++ for hardware modeling is important in providing the ability to integrate software and conduct architectural tradeoff among hardware and software blocks.
Linking software with the transaction level platform is done by integrating it with a processor model, such as ISS (Instruction Set Simulator) or by connecting it to a host (Host Code Execution), depending on the required processor model speed and accuracy needed.
A transaction level platform should be able to link with any processor and software development environment. It can create a virtual platform that is handed over to software developers that can validate and debug software against a hardware model even before RTL is implemented.