Reducing Cycle Time in Physical Verification

In the IC industry, profitability depends on rapid time-to-market and high manufacturing yield. As critical dimensions shrink below 65nm, yield becomes more sensitive to manufacturing variability. More complex and numerous design rule checks (DRCs) are needed to ensure designs can be efficiently realized in fabrication. At the same time, the sheer size of new designs causes DRC run times to grow exponentially. More complex design rules result in many more DRC violations that are more difficult to find, so engineers must spend more time fixing and re-checking their physical designs. All these factors extend the length of time to signoff. The situation can be improved by several technologies recently introduced in the Calibre product line. Next-generation Hyperscaling technology distributes design rule checking even more efficiently over many CPUs, providing more efficient memory and CPU usage and corresponding runtime reductions. New LVS analysis and debug features includes a graphical environment that’s easier to use and has advanced capabilities such as design-fix suggestions and visual indication of the location of geometrical and electrical violations, such as shorts in the layout. A dynamic results viewing environment allows designers to see violations and start fixing them as soon as they are detected, rather than waiting until the DRC run completes. Incremental DRC accelerates the workflow of signoff by allowing designers to fix and re-submit portions of a design for DRC checking in parallel.

Date/Time: August 28, 2008:

  • 7:00 am PDT (Aug. 28 - 14:00 GMT)
  • 1:00 pm PDT (Aug. 28 - 20:00 GMT)
  • 6:00 pm PDT (Aug. 29 - 01:00 GMT)

What you will Learn:

Attend this live webex and learn how to accelerate time to signoff using advanced techniques for physical verification.

Topics Include:

 

  • Turnaround Time
  • Debug Efficiency
  • Complex Design Checking

 

Who should attend:

 

  • Design Engineers/Managers
  • CAD Engineers/Managers

 

Featured products: nmLVS, nmDRC, RVE, Incremental DRC

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