Mentor at the 46th Annual Design Automation Conference (DAC)
The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.
Visit the Mentor Graphics booth, number 3567, to learn more about our software and hardware design solutions focused on IC design, place & route, physical verification, functional verification, FPGA/PLD, silicon test and yield analysis, PCB design, embedded software and emerging technologies such as ESL design and verification, system modeling and thermal analysis; and our innovative solutions that solve demanding design challenges such as low power and manufacturing variability.
Keynote Panel Discussion
Futures for EDA: The CEO View
Walden C. Rhines, Chairman & CEO, Mentor Graphics
DAC opens with a special Monday afternoon panel that brings together the CEOs of the leading EDA companies.
The panel will discuss the IC design and EDA ecosystem that has experienced many structural and financial upheavals in recent years. Perennial challenges – new technologies and markets, R&D investment levels, business and revenue models, and interoperability – are magnified by the current economic downturn.
Special Plenary Panel: How Green Is My Silicon Valley
Chair: Walden C. Rhines - EDA Consortium, Chair - Mentor Graphics Corp., Wilsonville, OR
There has been a lot of talk about ‘green’ technology, and how it can save our economy and the electronics industry. But what is really being done about it in Silicon Valley? This panel of experts, drawn from technology heavyweights, governmental agencies, venture capitalists and startups, will give their views on what ‘green’ means for our industry.
Networking Opportunity
Network with your peers at the Mentor booth Monday through Wednesday from 5:00 to 6:00 p.m.
More Mentor @DAC
DAC Lunch & Learn: Partnering for DFM Compliant IP Seminar
This year at DAC, Mentor Graphics, Chartered and ARM are working together to provide a unique perspective on optimizing third-party IP DFM robustness. Register Now
ESL Driving Forces: The Art of Architecture Design and Verification
This 7th Annual ESL Symposium at DAC is moderated this year by Walden C. Rhines, CEO Mentor Graphics, who will be joined by a panel of industry experts sharing their insight and knowledge. Register Now
Mentor’s Suite Sessions at DAC
- Accelerating SystemVerilog Testbenches Using Hardware Emulation
- Analog/Mixed-signal Verification Products Vision and Roadmap
- Beyond Physical Verification—Programmable Electrical Rule Checking (PERC)
- Catapult C Synthesis: Decisive Innovations for Low-Power and Full-chip Synthesis
- Catapult C User Perspectives (Japanese Language)
- Chip-Package-Board Co-Design and Advanced Packaging
- Custom IC Design and Verification Product Vision and Roadmap
- Design of Efficient Signal Processing Hardware using High Level Synthesis - Presented by Nitin Chawla, STMicroelectronics
- DFM — Surviving Adolescence and Moving Forward in the Design Flow
- ESL: The Art of Architecture Design and Prototype
- Improving System Productivity Through xtUML Models & Flexible Code Generation
- Integrated Calibre DRC/DFM Signoff Closure in Olympus-SoC P&R System
- Low Power SoC Verification with a UPF-Based Flow
- Manufacturing Variability and its Impact on Timing and Power
- Mentor Graphics' Silicon Test Solutions
- OVM: The Methodology Platform
- Rapid IC Implementation for Low-Power Mobile Devices
- Synthesis Unifies an FPGA Design Methodology from Concept to Layout
- SystemVerilog Verification from Requirements to Coverage Closure
- The New Paradigm for Physical Verification
- Verifying IP in Complex SoC Designs