Mentor Graphics at the 2011 Design Automation Conference (DAC)
Visit Mentor Graphics at booth 1542 to learn more about our wide range of software and hardware design solutions focused on electronic design and embedded software.
Highlights
Technical Panel: Double Trouble or Double Your Fun: Double-Patterning and Variability
The semiconductor industry faces extraordinary uncertainties at 20nm. The most pressing is what type of double-patterning to use and its impact on the entire flow. In addition, new device architectures and the explosion of variability and reliability effects must be managed. Panelists will discuss the critical risk factors at 20nm, the solutions that make the most dollars (and sense), and who should deliver those solutions.
Moderated by: Joe Sawicki, VP and GM, Design-to-Silicon Division
Technical Panel: 3-D - Devils, Details, and Debate
What a difference a year makes! It looks like 3-D has finally turned the corner with consumer products planned for the 32nm (or is it 28nm?) node. But devilish details — such as known-good die, standards, EDA tools, and flow signoff — could still become a showstopper. Panelists across the design ecosystem will shed light on which issues are still “devils” and those that are mere “details.”
Panelist: Janusz Rajski
New Panel: Who Is Driving 3D IC and Why?
While Moore's Law may be alive and well, it's certainly not cheap! Is the cost of IC scaling reaching a point of diminishing returns? With new 3D scaling alternatives such as Through Silicon Vias (TSV), does it make more sense to "go vertical" like real estate in Manhattan? This panel will host a discussion on the key issues surrounding 3D multi-die packaging, which affects everything from system design through IC implementation and testing. As 3D IC evolves over the next five years, what are the economic, performance, and power tradeoffs? Are we really ready for TSV in production? How will it affect the design, verification and testing flows? Plus many more questions that attendees are sure to pose to the panelists.
Moderator: Paul Dempsey, Editor-In-Chief, EDA Tech Forum Journal
Panelists:
- Sanjeev Sathe, GLOBALFOUNDRIES
- Mike Gianfagna, VP Marketing, Atrenta
- Simon Burke, Distinguished Engineer, Xilinx
- Juan Rey, Senior Engineering Director, Design to Silicon Division, Mentor Graphics
9th Annual ESL Symposium Panel
This panel examines the industry-wide move to ESL by highlighting the views and experiences of executives from leading system companies and EDA suppliers. Discussion will focus on the increase in system complexity that threatens to ignite a surge in the cost of design and verification. This cost has the potential to become untenable unless traditional design methods and flows are replaced with new design methodologies including, but not limited to Architectural Design, Virtual Prototyping, TLM Verification and High Level Synthesis.
Moderator: Wally Rhines, Chief Executive Officer and Chairman of the Board of Directors, Mentor Graphics
Panelists:
- Gadi Singer, Vice President, Intel Architecture Group and General Manager, System-on-Chip Enabling Group, Intel
- John Goodenough, Vice President, Design Technology and Automation, ARM
- Ken Hansen, Sr. Fellow, Vice President and Chief Technology Officer, Freescale
- Philippe Magarshack, Group Vice President, Technology R&D and General Manager, Central CAD and Design Solutions, STMicroelectronics
- Simon Bloch, Vice President and General Manager, Design to Synthesis Division, Mentor Graphics
Technical Panel: EDA Research - Stalled, Driving in Circles or Running out of Gas?
Everyone seems frustrated with the inefficiencies in EDA Research. So who’s to blame, and more importantly, who should fix it? One answer is that industry vendors need to take a more active role in supporting research. Or, should researchers focus more on real-world problems instead of generating papers? Come watch as these constituencies defend themselves, and in the end, you’ll decide who is wasting gas!
Panelist: Shankar Krishnamoorthy
New Panel: DFM Goes Mainstream...Are You Ready?
Design-for-Manufacturing comprises a broad range of tools and methodologies to minimize systematic defects and improve both functional and parametric yield. The importance and challenge of DFM increases at each technology node, and techniques are continuously evolving. Industry experts from all parts of the ecosystem will discuss DFM requirements, methods, tooling and experiences at 28nm. Essentially this will be a quick primer on what designers need to prepare for at advanced nodes.
Moderator: Paul Dempsey, Editor-In-Chief, EDA Tech Forum Journal
Panelists:
- Luigi Capodieci , Director DFM/CAD-R&D Fellow, GLOBALFOUNDRIES
- Dave Pietromonaco, Principal Engineer, ARM
- Mark Redford, VP U.S. Operations, CSR
- Jean-Marie Brunet, Director Product Marketing for Model Based DFM and Place-and-Route Integration, Mentor Graphics
Enter to win an Xbox Kinect
At DAC, look in your badge holder for the Mentor Graphics “Connect with Mentor” contest. Complete the card and drop off at our booth #1542. You will be eligible to win an Xbox® Kinect®. Daily drawings will be held at 10:55, 1:55 and 3:55.
Join us for our networking session daily at 4:00 p.m. Complimentary wine and beer will be served. Tuesday we will be featuring an open dialog with verification experts Harry Foster and Tom Fitzpatrick.
See you at our booth 1542 in San Diego!
Other Cool Events at DAC
-
DAC Workshop on Parallel Algorithms, Programming, and Architectures (PAPA)
Sunday, June 5, 9:00 AM — 6:00 PM, Room: 29ABThe primary goal of the workshop is to bring together three main categories of parallelism researchers to improve the understanding of progress and open problems in the cross-coupled fields of programming, algorithms, and architectures.
Presented by Duaine Pryor
-
DAC Workshop on Intra and Inter-Vehicle Networking: Past, Present, and Future
Sunday, June 5, 9:00 AM — 5:00 PM, Room: 29CDThis workshop focuses on the past, present, and potential future landscape of intra and inter-vehicle communication technologies, including CAN, FlexRay, Ethernet, and DSRC, with emphasis on the potential opportunities for the EDA industry in providing tool support for the analysis and design of Ethernet and DSRC based automotive architectures.
Presented by Bill Chown
-
DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems
Sunday, June 5, 10:00 AM — 1:00 PM, Room: 33AThis workshop, presented by expert verification methodology architects and engineers, will provide an example-based overview of UVM to chip and SOC design and verification engineers of all skill levels on the first open-source verification methodology to be fully supported and endorsed by all major EDA vendors, and many end-user and consulting companies.
Presented by Tom Fitzpatrick
-
A Designer's Guide to Sub-Resolution Lithography: Enabling the Impossible to get to the 15nm Node
Monday, June 6, 8:30 AM — 10:30 AM, 11:30 AM — 1:30 PM, 3:30 PM — 5:30 PM, Room: 33AThis short course will introduce the attendee to the principles of lithography scaling, explain the fundamental resolution limits and computational techniques implemented to overcome them, and help develop a thorough understanding of the increasingly severe design implications of sub-resolution patterning as we push towards the 15nm technology node.
Presented by Andres Torres
-
C-to-FPGA Tools: Ready for the Mass Market?
Tuesday, June 7, 1:00 PM — 1:45 PM, Booth: 3421FPGAs are no longer just used by logic designers. Embedded designers and algorithm developers place FPGAs at the heart of their designs. For FPGA vendors to capitalize on the market, viable C-to-FPGA tools are required. Is the current batch of tools up to the task? What are the FPGA and EDA vendors doing to serve this broad user base?
Panelist: Shawn McCloud
-
3-D Extraction: Coming to a Design Near You?
Tuesday, June 7, 3:00 PM — 3:45 PM, Booth: 3421Smaller IC geometries and higher switching speeds require more accurate modeling and simulation technologies. Traditional pattern-based matching and rule-based extraction methods may not be accurate enough for today’s IC and package designs. 3-D extraction tool providers and designers will discuss 3-D field solver technology requirements, applications, and benefits.
Presented by Carey Robertson
-
Mentor & TSMC: Improving Circuit Verification at Advanced Nodes With iLVS
Monday, June 6, 12:00 PM - 1:30 PM US/Pacific
Lunch will be providedJoin Mentor Graphics and TSMC at this DAC luncheon presentation as we discuss, iLVS, our collaboration for improved circuit verification at advanced nodes.
Accurate, comprehensive device recognition, connectivity extraction, netlist generation and, ultimately, circuit comparison becomes more complex with each new process generation. The number of layers and layer derivations are increasing and the complexity for device models, especially Layout Dependent Effects (LDS) becomes harder and harder to model. In the past, customers could take a foundry rule deck and easily modify to include their own devices (transistors, resistor, capacitors, inductors, etc.) with their own models and even augment with their own checks for ERC, etc. At 40nm, 28nm, few customers are able to do this confidently.
iLVS is a syntax that is the outcome of collaboration with TSMC and Mentor Graphics to provide customers a more easily adaptable solution to their circuit verification needs. Users can more easily modify and augment foundry rule decks yet still adhere to the modeling and manufacturing intent captured in these decks.
Learn more
MENTOR SUITE SESSIONS AT DAC
- A New Method to Accelerate the Yield Ramp
- Build and execute Virtual Platforms More Quickly with System Modeling, using BridgePoint and Vista
- Calibre Circuit Extraction at 20nm
- Catapult C Synthesis: The Why, What and How of High-Level Synthesis
- Custom IC Design Product Vision and Roadmap Customer Successes with Olympus-SoC
- Design to Silicon Division Highlights
- DFM State of the Art at 20nm
- Double Patterning for 20nm
- Eldo Premier: Boosted SPICE Simulation
- Everything You Ever Wanted to Know About the UVM But Were Afarid to Ask
- HDL & ESL Design Creation from Concept to Implementation to Compliance
- It’s All Connected: FPGA design, Implementation, Verification, and PCB
- Meeting the Challenges of 3D IC Verification Today
- Mentor Embedded Software: Proven Technology for Tomorrow’s Products
- Mentor ESL flow for TSMC Reference Flow 12
- New Approaches to Circuit Reliability
- New Automated Methods for Rad-Tolerant & Safety-Critical FPGA Design
- Olympus: Maximizing Value at 40/28nm and Getting Ready for 20 nm
- Overcoming Complexity in the Signoff Process at 20nm
- PANEL: DFM Goes Mainstream: Are You Ready?
- PANEL: Who Is Driving 3D IC and Why?
- Signoff-driven Custom Physical Design
- Tessent Support for 3D IC Testing
- Tessent Support of ARM Cores: Comprehensive and Integrated Test Solutions
- The Calibre Interface
- The Questa Platform: 100x faster functional Coverage Closure with Questa Ultra
- The Questa Platform: Power Management Verification with Questa
- The Questa Platform: Process, tools and Data Management, Reduce Risk, Improve Visibility and Control with Questa
- TLM Synthesis and Hardware Aware Virtual Platforms with Catapult C Synthesis
- Using xACT 3D to Optimize Complex Designs
- Verification Academy Unplugged: Formal Methods Not Just For Experts Anymore
- Verification Academy Unplugged: Integrating Assertion-Based Verification into Your Flow
- Vista for ESL Multicore Low-power Design
- Vista Virtual Prototyping
- What’s New in our Analog/Mixed-Signal Design and Verification Flow
- Why Companies Choose HW Emulation: Key Factors to Consider