Mentor at the 46th Annual Design Automation Conference (DAC)
The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.
Visit the Mentor Graphics booth, number 3567, to learn more about our software and hardware design solutions focused on IC design, place & route, physical verification, functional verification, FPGA/PLD, silicon test and yield analysis, PCB design, embedded software and emerging technologies such as ESL design and verification, system modeling and thermal analysis; and our innovative solutions that solve demanding design challenges such as low power and manufacturing variability.
Keynote Panel Discussion : Futures for EDA: The CEO View
Walden C.Rhines, Chairman & CEO, Mentor Graphics Corp.
DAC opens with a special Monday afternoon panel that brings together the CEOs of the leading EDA companies.
The panel will discuss the IC design and EDA ecosystem that has experienced many structural and financial upheavals in recent years. Perennial challenges – new technologies and markets, R&D investment levels, business and revenue models, and interoperability – are magnified by the current economic downturn.
Networking Opportunity
Network with your peers at the Mentor booth Monday through Wednesday from 5:00 to 6:00 p.m.
Special Plenary Panel: How Green Is My Silicon Valley
Chair: Walden C. Rhines - EDA Consortium, Chair - Mentor Graphics Corp., Wilsonville, OR
Multimedia
Wally Rhines talks about the Special Planetary Panel "How Green is My Silicon Valley?"
Technology Overview: There has been a lot of talk about ‘green’ technology, and how it can save our economy and the electronics industry. But what is really being done about it in Silicon Valley? View Video
Attend and be eligible to win one of these 'green' prizes - a Voltaic solar backpack, a Kiwi fuel saving device or a TED - The Energy Detective.
From the Mentor Blogs
DAC Highlight: Unified EDA Roadmap? and thoughts on "the next DFM"
blog post: So, I’ve “volunteered” to provide the occassional highlight of my DAC experience this year for Mentor Graphics. I was a little concerned about this, as I’ve been affraid this was going to be a rather lack-lustre…View Blog Post
46th DAC / STMicroelectronics designs a Frequency Domain Processor out of pure C++
blog post:
A couple of hours after Hitachi Telecom’s inspiring presentation on a 2 million gate enhanced Forward-Error Correcting (FEC) system design with Catapult C, Nitin Chawla of STMicroelectronics gave extensive…View Blog Post
46th DAC / Hitachi reports 8 tape-outs with Catapult C
blog post:
Looking at my San Francisco schedule, Tuesday was clearly the day I was most looking forward to. Besides the usual panels and meetings, I was really eager to hear the two testimonials from Hitachi…View Blog Post
Mentor’s Suite Sessions at DAC
- Accelerating SystemVerilog Testbenches Using Hardware Emulation
- Analog/Mixed-signal Verification Products Vision and Roadmap
- Beyond Physical Verification—Programmable Electrical Rule Checking (PERC)
- Catapult C Synthesis: Decisive Innovations for Low-Power and Full-chip Synthesis
- Achievements Using C Synthesis for Designs Too Complex to Code Manually
- Chip-Package-Board Co-Design and Advanced Packaging
- Custom IC Design and Verification Product Vision and Roadmap
- Design of Efficient Signal Processing Hardware using High Level Synthesis - Presented by Nitin Chawla, STMicroelectronics
- DFM — Surviving Adolescence and Moving Forward in the Design Flow
- ESL: The Art of Architecture Design and Prototype
- Improving System Productivity Through xtUML Models & Flexible Code Generation
- Integrated Calibre DRC/DFM Signoff Closure in Olympus-SoC P&R System
- Low Power SoC Verification with a UPF-Based Flow
- Manufacturing Variability and its Impact on Timing and Power
- Mentor Graphics' Silicon Test Solutions
- OVM: The Methodology Platform
- Rapid IC Implementation for Low-Power Mobile Devices
- Synthesis Unifies an FPGA Design Methodology from Concept to Layout
- SystemVerilog Verification from Requirements to Coverage Closure
- The New Paradigm for Physical Verification
- Verifying IP in Complex SoC Designs