Back to the Future: Is There Success without Moore's Law?
Panel Michael Buehler-Garcia, Senior Director of Marketing for Calibre Design Solutions
Monday, June 2, 4:00 p.m.
This panel will look at the ways that IC innovators are adding value to established IC nodes through increasing functionality, reduced power consumption, higher reliability, integration of MEMS and silicon photonics, and die stacking.
What will Moore's Law Cost Us at 10nm?
Panel Joe Sawicki, Vice President and General Manager Design to Silicon Division
Tuesday, June 3, 2014
For the first time in many years, there is a lot of uncertainty about how we get to the next IC scaling nodes. Will EUV be ready? Will we have to go to triple or quadruple patterning? Can DSA be commercialized quickly enough? What are the cost implications for these various alternatives? Can we see a way to get to 10nm and 7nm with an affordable technology? Are we at the point where designs are so tightly linked to a manufacturer’s specific process that multi-sourcing is unfeasible? How much commonality is there, and what can tools do to hide the differences? If it’s doable, is multi-sourcing economically viable? This panel will consider these all important questions and provide some insights if not the final answers.
Tackling FinFET Analog Mixed Signal and Memory Verification
Wednesday, June 2, 4:00 p.m.
Analog, mixed-signal, and SRAM design teams migrating to FinFET process nodes are implementing new architectures to take advantage of FinFET benefits and overcome its limitations. As a result they need to retool their transistor-level verification flow for more accuracy, performance and capacity to offset the increased layout, device modeling, device noise, voltage scaling, and process variation effects. Designers of complex analog/mixed-signal circuits such as PLLs, ADCs, SerDes, and transceivers, need to explore alternative architectures and measure their impact in non-planar silicon. Embedded SRAM design teams realize that it is no longer acceptable to tolerate 5% or more inaccuracy in memory IP characterization. This panel is an interactive forum where attendees can exchange ideas and questions with a group of experts who are tackling the exciting opportunities and challenges related to the move to FinFET nodes.
Mentor@DAC 2014 Events
We’ve brought some of our best researchers and partners to DAC just to meet you. Find your favorites in the list below. Then hurry and sign up for their sessions, before they fill up!
There’s nothing better than learning about the latest in cutting-edge design, while enjoying good food and socializing with your peers. Mentor puts on the most ‘seriously’ fun events daily, so make sure you get them on your calendar.
Come listen to our brightest researchers and executives discuss the latest design issues in the DAC Conference panels, tutorials, workshops, papers and in the user track.
Mentor Graphics offers the broadest support for the electronics ecosystem/supply chain. That’s why you’ll find Mentor experts sharing in a numerous partner activities on the exhibition floor—both in our booth and at our partners’ locations.
Technical Focus Areas
Mentor Graphics will be discussing the latest innovations in these key focus areas:
Celebrating Your Design Creativity!
Rejuvenate with free coffee drinks every day, and restore your creative juices with free wine and beer, 4-6 p.m. daily.
June 1–5, 2014
San Francisco, CA
Register for DAC
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