Angela Wong, Technical Marketing Engineer, Mentor Graphics
- Preparing for Pervasive Photonics Abstract
SUITE SESSION Silicon photonics is using silicon for the fabrication of light-based devices—such as lasers, amplifiers, converters, filters and splitters. Current applications include ultra-fast chip-to-chip optical interconnects, optical routers and signal processors. Visionaries see SP as an enabling technology that will impact many facets of life through entertainment, medical discovery, communications, information storage, and manufacturing. This session discusses the impact photonics will have on today’s IC design and manufacturing processes, the tool requirements for SP, foundry options, new applications that will SP open up, and new challenges it will present to IC designers. Tue 2:00, Mentor booth.
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Arvind Narayanan, Product Marketing Manager, Mentor Graphics
 Arvind Narayanan is a Product Marketing Manager in the Place and Route division at Mentor Graphics. Prior to Mentor Arvind has held various design, application engineering and marketing positions at Hal Computers, Synopsys and Magma. He has been an active particiapnt in the Unified Power Format initiative. He holds a Masters Degree in Electrical and Computer Engineering (Mississippi State University) and a Masters Degree in Business Administration (Duke University).
- Achieving Best PPA at Advanced Nodes using Olympus-SoC Abstract
PARTNER KIOSK PRESENTATION One of the predominant P&R challenges is realizing best power, performance and area (PPA), a goal that is more difficult to achieve at advanced nodes due to complex DRC / DFM rules, double patterning, growing design sizes, low power requirements and increasing process and design variations. It is also critical to reduce the die size to justify the cost of moving to smaller nodes. This session shows advanced technologies for efficient design closure such as concurrent PPA optimization, pseudo flat flow methodology and DRC/DP signoff during implementation. Tue 11:00 in the TSMC booth.
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Carey Robertson, Director of Product Marketing, Mentor Graphics
 Carey Robertson is a Director of Product Marketing at Mentor Graphics Corp., overseeing the marketing activities for Calibre PERC, LVS and extraction products. He has been with Mentor Graphics for 14 years in various product and technical marketing roles. Prior to Mentor Graphics, Carey was a design engineer at Digital Equipment Corp., working on microprocessor design. Carey holds a BS from Stanford University and an MS from UC Berkeley.
- Advanced Parasitic Extraction for 20nm/16nm and 3D-IC Abstract
SUITE SESSION The parasitic extraction flow is being challenged on a number of fronts: the need for higher accuracy at smaller dimensions, the complexity of high transistor and gate counts and more extensive fill, the impact of double patterning on modeling and accuracy, the need for new models for FinFETs and Through Silicon Via (TSVs), and the need to handle ECOs in an fast and efficient manner. This session will describe these new challenges and also new approaches to PEX that can deliver the required capabilities while significantly reducing turnaround time.
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- Panel: Achieving IC Reliability in High Growth Markets Abstract
SUITE PANEL Several high growth IC markets are experiencing demand for higher reliability, including mobile/wireless, automotive, industrial control and medical. At the same time, factors such as thinner gate oxide and multiple power rails have the potential to introduce subtle design flaws leading to delayed failure mechanisms. This panel will be an interactive forum where experts and attendees on the show floor can discuss the demand for IC reliability, what design methodologies can reduce the occurrence of delayed failure mechanisms, and how design for reliability checks can be automated to help remove the burden from designers. The panel will be immediately followed by a hosted bar happy hour.
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Frank Feng, Circuit Verification Methodologist, Mentor Graphics
 Frank Feng currently works at Mentor Graphics as a Circuit Verification Methodologist for the Calibre product line in the Design to Silicon division. Frank has over twelve years of experience in the EDA industry in the areas of layout and circuit verification and implementation, and four years of experience in semiconductor semi manufacturing. Frank holds a Ph.D. in Physics.
- Reliability Checks for Multiple Markets Abstract
SUITE SESSION Reliability issues usually require design verification driven from circuit schematics to the corresponding layout data. Traditional DRC engines can’t distinguish the specific functions of layout geometries, so manual markers are required to enable automated checks. However, erroneous markers can jeopardize reliability checking. Calibre PERC provides a fully automated and comprehensive EDA design platform to check ESD, latch-up, EOS, ERC and other design issues in both design and stream out databases. Calibre PERC is the first, and currently the only available tool with a qualified design kit from several major foundries for reliability signoff. In this session, to be presented in Mandarin, Mentor Graphics and Semiconductor Manufacturing International Corporation (SMIC) discuss reliability checking with Calibre PERC. Mon 10:00 in Mentor booth.
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Hellen Cheng, Senior Manager, IP Development Center, SMIC
 Hellen Cheng is senior manager of the IP Development Center at SMIC, where she is in charge of all in-house IO library development. She has nine years of experience in the semiconductor industry, having joined SMIC in 2003 to focus on library development and ESD design. Hellen also leads a company-wide ESD task force, which plays a key role in SMIC's ESD management strategy. Hellen graduated from Tsinghua University in 2003.
- Reliability Checks for Multiple Markets Abstract
SUITE SESSION Reliability issues usually require design verification driven from circuit schematics to the corresponding layout data. Traditional DRC engines can’t distinguish the specific functions of layout geometries, so manual markers are required to enable automated checks. However, erroneous markers can jeopardize reliability checking. Calibre PERC provides a fully automated and comprehensive EDA design platform to check ESD, latch-up, EOS, ERC and other design issues in both design and stream out databases. Calibre PERC is the first, and currently the only available tool with a qualified design kit from several major foundries for reliability signoff. In this session, to be presented in Mandarin, Mentor Graphics and Semiconductor Manufacturing International Corporation (SMIC) discuss reliability checking with Calibre PERC. Mon 10:00 in Mentor booth.
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Indavong Vongsavady, Director at ST Central CAD and Design Solutions, STMicroelectronics
- Panel: No Fear of FinFET Abstract
SUITE PANEL FinFETs, or so-called 3D transistors, are a key competitive element in all the leading edge IC foundry offerings because FinFETs can achieve much lower power operation than planar transistors. There has been a lot of discussion of the physical and electrical characteristics of FinFETs, but designers are wondering how FinFETs will change the design, verification and test flow. This show floor panel will provide a forum for experts and DAC attendees to learn and interact directly in an informal and entertaining discussion. The panel will be immediately followed by a hosted bar happy hour.
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Jean-Marie Brunet, Director of Product Marketing, DFM and Place-and-Route Integration, Mentor Graphics
 Jean-Marie Brunet is the Director Product Marketing for Model Based DFM and Place-and-Route Integration at Mentor Graphics Corporation. Over the past 18 years, he has served in application engineering, marketing and management roles in the EDA industry, and has held IC design and design management positions at STMicrolectronics, Cadence, and Micron among others. His experience includes working with pure-play foundries to resolve complex yield issues related to OPC and RET. He holds a Master's degree in Electrical Engineering from I.S.E.N Electronic Engineering School in Lille, France.
- DFM at Advanced Nodes Abstract
SUITE SESSION At 28 nm and below, litho process checking (LPC), CMP analysis and critical area analysis (CAA) are all crucial steps to help ensure manufacturability. In addition, layout fill has become a more complex and critical issue. While in the past the goal was simply to insert minimum fill to maintain planarity, today you need to maximize fill and place and orient it precisely to optimize its benefits. Come to this session to understand today’s DFM issues, to find out what is required by the foundries at each node, to learn about updates to DFM tools, and to see how SmartFill is changing the approach to fill at advanced nodes.
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Joe Sawicki, Vice President & General Manager, Design-to-Silicon Division, Mentor Graphics
 Sawicki is the vice president and general manager of the Design-to-Silicon division. A leading expert in IC nanometer design and manufacturing challenges, Sawicki is responsible for Mentor's industry-leading design-to-silicon products, including the Calibre physical verification and DFM platform and Mentor's Tessent design-for-test product line. Sawicki joined Mentor Graphics in 1990 and has held previous positions in applications engineering, sales, marketing and management. He holds a BSEE from the University of Rochester, an MBA from Northeastern University's High Technology Program, and has completed the Harvard Business School Advanced Management Program.
- Panel: No Fear of FinFET Abstract
SUITE PANEL FinFETs, or so-called 3D transistors, are a key competitive element in all the leading edge IC foundry offerings because FinFETs can achieve much lower power operation than planar transistors. There has been a lot of discussion of the physical and electrical characteristics of FinFETs, but designers are wondering how FinFETs will change the design, verification and test flow. This show floor panel will provide a forum for experts and DAC attendees to learn and interact directly in an informal and entertaining discussion. The panel will be immediately followed by a hosted bar happy hour.
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John Ferguson, Director of Marketing, Mentor Graphics
 John Ferguson is the Lead Technical Marketing Engineer for the Calibre product line at Mentor Graphics in Wilsonville, Oregon. He received a BS degree in Physics from McGill University in 1991, an MS in Applied Physics from the University of Massachusetts in 1993, and a PhD in Electrical Engineering from the Oregon Graduate Institute of Science and Technology in 2000. He has worked extensively in the area of physical design verification.
- Best Practices for 20nm Design Abstract
SUITE SESSION When leading edge customers first transitioned to 20nm they encountered issues not experienced in prior nodes with the set-up of hardware, flows, and use models during chip verification. TSMC and Mentor worked with these customers to resolve the issues resulting in successful tape-outs of these customers’ designs. TSMC and Mentor will present best practices learned from that experience to help other customers smoothly tape-out their advanced process node designs. Mon 2:00, Mentor booth.
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Joseph Adesanya, ASIC Design Manager, Ostendo Technologies
 Joseph Adesanya works at Ostendo Technologies as the ASIC System’s Manager and his core duties encompassed all phases of product development; from specification and architectural design, down to FPGA prototyping and ASIC hardening. Before joining Ostendo, Joseph worked at General Atomics as a principal staff engineer where he worked on Ultra Wide Band (UWB) based solutions ranging from unattended ground sensor networks to USB and streaming media applications. Prior to General Atomics, Joseph has held ASIC lead positions at Hughes Network Systems and Nokia Telecommunications (Finland). Joseph holds a MSC degree in Mobile, Personal and Satellite Communications and a BENG degree in Electrical and Electronics Engineering from the University of Westminster (UK). He is a senior member of Institute of Electrical and Electronics Engineers (IEEE) and a member of the Institution of Engineering and Technology (IET).
- Implementing a Quantum Photonic Imager using Olympus-SoC Abstract
SUITE SESSION Designing a quantum photonic imagers poses a unique challenge to the P&R designers due to the inherent nature of the stacked die interface. This technology has a high density of signal interfaces driven by Analog macros that pose a big challenge during P&R from both a floorplanning and routing perspective. This session will talk about the full netlist to GDS implementation of the photonic imager design done using Olympus. The session will also cover how Olympus was able to handle the unique design requirements specifically from a floorplanning and routing standpoint, and was able to successfully achieve design closure.
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Karthik Sundaram, Senior Hardware Engineer, Nvidia Corporation
 Karthik Sundaram is a Senior Hardware Design Engineer at Nvidia. He has a Bachelor of Science Degree from College of Engineering, Anna University (India) and Master of Science degree in Electrical Engineering from University of Cincinnati. Before joining Nvidia he was a VLSI design engineer at Wipro Technologies (India). He is a seasoned design veteran with over 9 years of industry experience.
- Efficient Chip Assembly & Design Closure flow for large GPUs & Tegras using Olympus-SoC Abstract
SUITE SESSION With the growing design sizes at advanced nodes, top level chip assembly and optimization is done using abstracts without the full chip context. This is an highly iterative and manual process that can have a noticeable huge impact on design turn-around time and QoR. In this session we will discuss the chip assembly solution from Olympus-SoC P&R platfomr including key technologies such as top level concurrent MCMM optimization, Synchronous optimization for replicated partitions, top level clock tuning and layer promotion of critical nets for faster timing convergence and design closure.
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Ken Amstutz, Sr. Application Engineer, Mentor Graphics
Ken Amstutz is a Sr. Application Engineering Consultant at Mentor Graphics in Austin, TX. He has been assisting leading semiconductor companies solving design-for-test (DFT) challenges for the past 15 years. His current focus is on automatic test pattern generation (ATPG), diagnosis, and yield analysis.
- Identifying Critical Design Features from Silicon Results Abstract
PARTNER KIOSK PRESENTATION The ability to effectively identify yield limiting design feature is a key asset for foundries and fabless semiconductor companies. This presentation covers the result of a collaboration between Mentor Graphics and GLOBALFOUNDRIES to rapidly identify systematic defects and critical design features based on silicon data [1-4]. Layout-aware diagnosis identifies the location and classification of defects causing manufacturing test failures. Specialized statistical analysis coupled with design profiling data (such as critical feature analysis) then determines the root cause of yield loss and separates design and process induced defects. Tue 10:00 in the GLOBALFOUNDRIES booth.
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KK Lin, Director of Design Enablement, Samsung
- Panel: No Fear of FinFET Abstract
SUITE PANEL FinFETs, or so-called 3D transistors, are a key competitive element in all the leading edge IC foundry offerings because FinFETs can achieve much lower power operation than planar transistors. There has been a lot of discussion of the physical and electrical characteristics of FinFETs, but designers are wondering how FinFETs will change the design, verification and test flow. This show floor panel will provide a forum for experts and DAC attendees to learn and interact directly in an informal and entertaining discussion. The panel will be immediately followed by a hosted bar happy hour.
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Matthew Hogan, Product Marketing Manager, Calibre Design Solutions, Mentor Graphics
 Matthew Hogan is a Product Marketing Manager for Calibre Design Solutions at Mentor Graphics, with over 15 years of design and field experience. He is an IEEE Senior member and ACM member and holds a Bachelor of Engineering from the Royal Melbourne Institute of Technology and an MBA from Marylhurst University. He is actively working with customers who have an interest in Calibre PERC.
- Advancing Circuit Reliability at TowerJazz with Calibre PERC Rule Decks Abstract
SUITE SESSION TowerJazz, the global specialty foundry leader, is now providing Calibre PERC rule decks that enable their customers to perform circuit reliability verification during signoff. TowerJazz provides highly customized electrostatic discharge (ESD) and power management circuit checks based on their specific manufacturing processes. Many of these checks have been automated for the first time by taking advantage of the Calibre PERC product’s unique ability to combine schematic (net list) and physical layout information, which goes beyond the scope of traditional LVS, DRC and ERC tools. This is a one-time, limited seating session for advanced Calibre users. Tue 2:00, Mentor booth.
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Michael Buehler-Gracia, Director of Marketing for Calibre Design Solutions, Mentor Graphics
 Michael Buehler-Garcia is the Director of Marketing for Calibre Design Solutions in the Design-to-Silicon Division of Mentor Graphics. He manages all aspects of marketing for Calibre design-side product offerings, including product and tactical marketing efforts, strategic positioning, and integration to other business units within Mentor's Design to Silicon organization. Mr. Buehler has experience in all facets of the semiconductor eco-system, including EDA companies, foundries, fabless companies, and their end customers. He has over 25 years of experience, including executive positions at companies such as iRoC Technologies and PDF Solutions, as well as Chartered Semiconductor, one of the largest foundries in the world, and Cadence Design Systems, one of the world's largest EDA companies. He brings a unique perspective for optimizing and leveraging supply chains, along with expertise of how both multinational and start-up companies can succeed in the new world of outsourcing all elements of a company. Coupled with this hands-on knowledge is the capability to create and drive overall company strategic direction from endgame strategies to the underlying product roadmap and definition.
- Calibre Support for TSMC's 20nm Process Abstract
PARTNER KIOSK PRESENTATION Mentor will describe advances to support TSMC's 20nm IC processes. Calibre has a new engine with DP anchoring and pre-coloring, DP design rule checking, voltage-dependent checking and patented real-time graphical “error rings” to simplify fixing DP violations. A new 20nm Calibre PERC deck addresses potential reliability issues such as ESD and latch-up. Calibre SmartFill optimizes filling while ensuring that overall run times and files sizes are controlled. The Calibre LFD™ product works with the TSMC Unified DFM Engine, incorporating Calibre Pattern Matching technology to accelerate the litho hot spot detection. Mon 2:30 in the TSMC booth.
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Michael Hochberg, Director, OpSIS, University of Delaware
 Michael Hochberg is a co-founder of Luxtera, a photonics component firm, and also directs OpSIS, a foundry service for silicon photonics in which the community shares the cost of fabricating complex chip-scale systems across many projects. A longtime photonics reasearcher, Hochberg's work has been featured in Nature Materials, Nature, and other journals.
- Panel: Marrying More Than Moore Abstract
SUITE PANEL The IC industry will undergo significant changes as future growth is driven not just by traditional Moore’s Law scaling, but also by “More Than Moore” technologies including 3D-IC, MEMS and silicon photonics. As these technologies emerge from R&D into volume production, they will create new opportunities for IC designers to add value to products. They will also challenge designers to find a way to combine the strengths of these technologies and to marry them into a unified EDA flow. This panel will be an interactive forum where attendees on the exhibition floor can exchange ideas and questions with a group of experts who are already grappling with these exciting opportunities and challenges. The panel will be immediately followed by a hosted bar happy hour.
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Michael White, Director of Product Marketing, Calibre Physical Verification products, Mentor Graphics
 Michael White is the Director of Product Marketing for Mentor Graphics' Calibre Physical Verification products. Prior to Mentor Graphics, he held various product marketing, strategic marketing and program management roles for Applied Materials, Etec Systems and the Lockheed Skunk Works. Michael received an MS in engineering management from the University of Southern California MBA School, and a BS in System Engineering from Harvey Mudd College.
- Physical Verification with Multi-Patterning for Advanced Nodes Abstract
SUITE SESSION Physical verification (PV) complexity continues to grow by leaps and bounds as customers move to the advanced nodes that require multi-patterning. Come learn about the emerging trends in PV and how the Calibre nmPlatform continues to rapidly expand, addressing the needs for advanced PV and helping you get your design to market faster.
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Ofer Tamir, Director of Design Enablement and Design Support, TowerJazz
 Ofer Tamir is the Director of design enablement and design support at TowerJazz. He has a Master’s Degree in computer science and has worked for 25 years as an EDA engineer at companies such as National Semiconductor (CAD engineer & CAD/ layout verification) and DSPG (CAD manager).
- Advancing Circuit Reliability at TowerJazz with Calibre PERC Rule Decks Abstract
SUITE SESSION TowerJazz, the global specialty foundry leader, is now providing Calibre PERC rule decks that enable their customers to perform circuit reliability verification during signoff. TowerJazz provides highly customized electrostatic discharge (ESD) and power management circuit checks based on their specific manufacturing processes. Many of these checks have been automated for the first time by taking advantage of the Calibre PERC product’s unique ability to combine schematic (net list) and physical layout information, which goes beyond the scope of traditional LVS, DRC and ERC tools. This is a one-time, limited seating session for advanced Calibre users. Tue 2:00, Mentor booth.
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Prashant Varshney, Product Engineering Director, Mentor Graphics
 Prashant Varshney has over 15 years of experience in Semiconductor and EDA industry with a successful track record of hardware and software product development, deployment and proliferation. Starting his career at the transistor level design at Duet Technologies, Prashant worked his way to a component design engineer at Intel Corporation in 1999, designing and implementing multiple networking ASIC products. Later in 2003, Prashant became a part of a then stealth startup, Sierra Design Automation, making significant contributions to design, deployment and marketing of their innovative product line, while managing their product engineering team. During the 10 years of association with the place and route product line of Mentor Graphics, Prashant has led multiple sales campaigns resulting in both technical and financial success. He has built from scratch and now leads multiple large cross-functional, cross-site teams, and is responsible for product engineering, flow and methodology development, product validation and configuration management functions for the Place and Route Division. Prashant holds a MSEE from Stanford University.
- Achieving Best PPA at Advanced Nodes using Olympus-SoC Abstract
PARTNER KIOSK PRESENTATION One of the predominant P&R challenges is realizing best power, performance and area (PPA), a goal that is more difficult to achieve at advanced nodes due to complex DRC / DFM rules, double patterning, growing design sizes, low power requirements and increasing process and design variations. It is also critical to reduce the die size to justify the cost of moving to smaller nodes. This session shows advanced technologies for efficient design closure such as concurrent PPA optimization, pseudo flat flow methodology and DRC/DP signoff during implementation. Tue 2:05 in the GLOBALFOUNDRIES booth.
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Randy Grover, Director, Product Development, Digital Convergence Group, ST Microelectronics
 Randy Grover has 29 years of experience in ASIC and SoC design, EDA development and technical sales support with STMicroelectronics, Texas Instruments, Cooper & Chyan Technology, and Cadence Design Systems. He has worked with a large variety of customer design organizations worldwide in both design engineering and management roles. Douglas holds BSEE (Computer Hardware Design) from Auburn University.
- Physical Design Flow Experience and Silicon Successes Using Olympus-SoC Abstract
SUITE SESSION In this session STMicroelectronics will be sharing their experience and successes in using Olympus-SoC on their designs. They will be specifically covering the key backend design challenges and how Olympus was effectively used for timing and design closure including MCMM based timing, and area optimization for their designs. Results and comparisons from case studies will be presented in the session
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Richard Trihy, Director Design Methodology, GLOBALFOUNDRIES
- Panel: No Fear of FinFET Abstract
SUITE PANEL FinFETs, or so-called 3D transistors, are a key competitive element in all the leading edge IC foundry offerings because FinFETs can achieve much lower power operation than planar transistors. There has been a lot of discussion of the physical and electrical characteristics of FinFETs, but designers are wondering how FinFETs will change the design, verification and test flow. This show floor panel will provide a forum for experts and DAC attendees to learn and interact directly in an informal and entertaining discussion. The panel will be immediately followed by a hosted bar happy hour.
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Robert Patti, CTO and VP of Design Engineering, Tezzaron
- Panel: Marrying More Than Moore Abstract
SUITE PANEL The IC industry will undergo significant changes as future growth is driven not just by traditional Moore’s Law scaling, but also by “More Than Moore” technologies including 3D-IC, MEMS and silicon photonics. As these technologies emerge from R&D into volume production, they will create new opportunities for IC designers to add value to products. They will also challenge designers to find a way to combine the strengths of these technologies and to marry them into a unified EDA flow. This panel will be an interactive forum where attendees on the exhibition floor can exchange ideas and questions with a group of experts who are already grappling with these exciting opportunities and challenges. The panel will be immediately followed by a hosted bar happy hour.
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Stephen Pateras, Product Marketing Director, Mentor Graphics
 Stephen Pateras is product marketing director for Mentor Graphics Silicon Test products. His previous position was VP Marketing at LogicVision. While at LogicVision Stephen also held senior management positions in engineering, and was instrumental in defining and bringing to market several generations of LogicVision’s semiconductor test products. From 1991 to 1995, Stephen held various engineering lead and management positions within IBM’s mainframe test group. He received his Ph.D. in Electrical Engineering from McGill University in Montreal, Canada
- DFT and Test for Safety Critical Applications Abstract
SUITE SESSION ISO 26262 is emerging as a standard that’s being rapidly adopted by the automotive industry. This standard specifies objectives that must be met in the development of safety critical automotive electronics systems. This standard is already starting to push new requirements down to the semiconductor suppliers for these automotive subsystems. This is creating an opportunity for automotive semiconductor suppliers to differentiate themselves based on their test strategy, which can make their offering more appealing for ISO 26262 mandated systems. This session will focus on features and solutions within Mentor Graphics’ Tessent silicon test and yield analysis products that can be leveraged for designs destined for an ISO 26262 application.
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Suk Lee, Senior Director Design Infrastructure Marketing Division, TSMC
 Mr. Suk Lee has 25 years of experience in the semiconductor and EDA industries and is currently Senior Director of Design Infrastructure Marketing Division at TSMC. He has held engineering, marketing, and management positions at LSI, Texas Instruments, Cadence, and Magma Design Systems. He holds a Bachelor of Engineering from MIT and Master of Science from the University of Toronto.
- Panel: Marrying More Than Moore Abstract
SUITE PANEL The IC industry will undergo significant changes as future growth is driven not just by traditional Moore’s Law scaling, but also by “More Than Moore” technologies including 3D-IC, MEMS and silicon photonics. As these technologies emerge from R&D into volume production, they will create new opportunities for IC designers to add value to products. They will also challenge designers to find a way to combine the strengths of these technologies and to marry them into a unified EDA flow. This panel will be an interactive forum where attendees on the exhibition floor can exchange ideas and questions with a group of experts who are already grappling with these exciting opportunities and challenges. The panel will be immediately followed by a hosted bar happy hour.
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Tim Turner, Reliability Center Business Development Manager, College of Nanoscale Science and Engineering, University at Albany, NY
- Panel: Achieving IC Reliability in High Growth Markets Abstract
SUITE PANEL Several high growth IC markets are experiencing demand for higher reliability, including mobile/wireless, automotive, industrial control and medical. At the same time, factors such as thinner gate oxide and multiple power rails have the potential to introduce subtle design flaws leading to delayed failure mechanisms. This panel will be an interactive forum where experts and attendees on the show floor can discuss the demand for IC reliability, what design methodologies can reduce the occurrence of delayed failure mechanisms, and how design for reliability checks can be automated to help remove the burden from designers. The panel will be immediately followed by a hosted bar happy hour.
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Yi-Kan Cheng, Deputy Director of the Design Methodology & Kit Development Division, TSMC
 Dr. Yi-Kan Cheng is the Deputy Director of the Design Methodology & Kit Development Division at TSMC, where he manages TSMC’s design methodology, Reference Flow, DFM, physical verification, RC extraction, and process design kit (PDK) development. He was with IBM and Intel from 1997 to 2005, where he worked on timing optimization and analysis, power analysis, IC reliability, and signal integrity aware design for high-performance microprocessors. Dr. Cheng received the Ph.D. EE/CE at the University of Illinois at Urbana-Champaign.
- Best Practices for 20nm Design Abstract
SUITE SESSION When leading edge customers first transitioned to 20nm they encountered issues not experienced in prior nodes with the set-up of hardware, flows, and use models during chip verification. TSMC and Mentor worked with these customers to resolve the issues resulting in successful tape-outs of these customers’ designs. TSMC and Mentor will present best practices learned from that experience to help other customers smoothly tape-out their advanced process node designs. Mon 2:00, Mentor booth.
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Ms. Burns has over 25 years of experience in the chip design and the EDA industries in various roles of engineering, applications engineering, technical marketing and product management. She is currently the Product Manager in the Design and Verification Technology Division at Mentor Graphics responsible for simulation with Questa and ModelSim. Prior to Mentor Graphics, Ms. Burns has held engineering and marketing positions at CoWare, Cadence, Synopsys, Viewlogic, Computervision and Intel. She holds a BSCpE from Oregon State University.
Jim Kenney has over 25 years of experience in hardware emulation and logic simulation and has spent the bulk of his career at Mentor Graphics Corporation. Jim has held responsibility for analog, digital and mixed-signal simulation, hardware/software co-verification and hardware emulation. He is currently the Marketing Director for Mentor's Emulation Division. Jim holds a BSEE from Clemson University.
Jon McDonald is Sr. Technical Marketing Engineer at Mentor Graphics. He received a BS in Electrical and Computer Engineering from Carnegie Mellon and an MS in Computer Science from Polytechnic University. He has been active in digital design, language based design and architectural modeling for over 15 years. Prior to joining Mentor Graphics Mr. McDonald held senior technical engineering positions with Summit Design, Viewlogic Systems and HHB Systems.
Roger Do is Synthesis Product Specialist at Mentor Graphics. He has over 16 years of FPGA experience, including previous roles in corporate and field applications and product marketing with Texas Instruments, Lucent Technologies, and Lattice Semiconductor. Roger holds a B.S. in Electrical Engineering from Texas A&M University.
Roger Sabbagh has over 19 years of experience in system and silicon design & verification, CAD methodology development and technical marketing. As a verification technologist at Mentor Graphics, Mr. Sabbagh is focused on the areas of assertion based verification, formal functional verification and clock-domain crossing verification. In this position, he works with leading edge silicon design teams to help them adopt advanced methodologies. Prior to joining Mentor, Mr. Sabbagh has held positions in CAD methodology and design at Nortel Networks and Worldheart. Mr. Sabbagh holds a bachelor degree in electrical engineering from Carleton University in Ottawa, Canada.
If there is something Mentor is not doing in the area of functional verification, but you think we should be, Steve wants to know about it. Steve is bringing his extensive experience spanning development of HDL simulators, applications engineering, consulting, and technical and product marketing to direct Mentor into new market opportunities for verification and coordinate between Mentor's verification-related divisions.
Dr. Subba Somanchi currently serves as Director of the System Modeling & Analysis business unit in the System-Level Engineering Division at Mentor Graphics. As such, he is responsible for the SystemVision and BridgePoint product lines. Somanchi has worked on SystemVision for the past 13 years, serving as Product Architect and Engineering Manager after holding the position of Staff Engineer. He also worked as a Model Development Engineer at Analogy, Inc., working on schematic-driven mechatronic simulation products. Somanchi holds a Ph.D. in Electrical Engineering from Washington State University and an MBA from Marylhurst University.
Valerie Rachko is the director of HDL & ESL design creation marketing in the Design Creation business unit of ESD, located in Wilsonville. Valerie has been marketing HDL design products for Mentor Graphics since 1990, ranging from creation, analysis, reuse, checking, verification, synthesis, and design management, with more recent expansion into UVM/OVM and ESL. She holds Bachelor of Science and Master of Science degrees in electrical engineering from Fairleigh Dickinson University, USA, graduating in both with summa cum laude honors. She is also a magma cum laude Master of Business Administration in marketing graduate from Seton Hall University, USA. Prior to joining Mentor Graphics, she was an ASIC designer for over five years.
Abhishek Ranjan is Senior Director of Engineering at Calypto Design Systems where he is responsible for development of the RTL power optimization product, PowerPro. Prior to Calypto, he held various leadership and management positions at Xilinx Inc., Hierarchical Design, and Monterey Design Systems. Abhishek received a Bachelor of Technology in Electrical Engineering from the Indian Institute of Technology, Kanpur, India. He holds a Master’s degree in Computer Engineering from Northwestern University, Illinois, USA. Abhishek holds several patents in the field of VLSI CAD and has published dozens of research papers in reputable conferences and journals.
Cliff Cummings is President of Sunburst Design, Inc., a company that specializes in world class Verilog, SystemVerilog and synthesis training. Mr. Cummings is an independent consultant and trainer with 27 years of ASIC, FPGA and system design experience and 17 years of Verilog, SystemVerilog, synthesis and methodology training experience. Mr. Cummings has completed many ASIC designs, FPGA designs and system simulation projects, and is capable of answering the very technical questions asked by experienced design engineers. Mr. Cummings, a member of the IEEE 1364 Verilog Standards Group since 1994, is the only Verilog and SystemVerilog trainer to help develop every IEEE and Accellera Verilog & SystemVerilog Standard. Mr. Cummings is also actively participating in the next IEEE Verilog & SystemVerilog Standards. Mr. Cummings, who holds a BSEE from Brigham Young University and an MSEE from Oregon State University, is a member of the IEEE, and the Eta Kappa Nu, Tau Beta Pi and Sigma Delta Pi Honor Societies.
Dennis B. Brophy is Director of Strategic Business Development at Mentor Graphic Corporation. He is also volunteer vice-chair and past chair of Accellera, an electronic design automation standardization group. Dennis has been in the electronic design automation industry for the past 33 years. He was first with Hewlett-Packard for five years, and then joined Mentor Graphics, where he has held several positions over the past 28 years. He is a member of the IEEE Standards Association (SA) Board of Governors (BoG) and Chair of the IEEE SA Corporate Advisory Group (CAG). He is secretary of the IEEE 1800 SystemVerilog Working Group and IEEE 1666 SystemC Working Group. Dennis is also a member of the American National Standards Institute (ANSI) and is a member of the United States National Committee for EDA standards. He is a co-convenor of IEC TC91 WG13. Dennis received a Bachelor of Science degree from the University of California at Davis in electrical engineering and computer engineering in 1980.
Harry Foster is Chief Scientist for Mentor Graphics' Design Verification Technology Division. He holds multiple patents in verification and has co-authored seven books on verification. Harry was the 2006 recipient of the Accellera Technical Excellence Award for his contributions in developing industry standards.
Mark Olen is currently a Functional Verification Technologist at Mentor Graphics Corp. He has spent over thirty years in semiconductor design verification and manufacturing test, and has authored papers in the areas of intelligent testbench automation, design for test technology, and semiconductor manufacturing test automation. He wrote his first testbench in 1981 at Raytheon, and went on to spend ten years working at Teradyne in the ATE and DFT industries. He became Vice President of Cascade Microtech's thin film wafer probe division, before co-founding Lighthouse Design Automation where graph-based Intelligent Testbench Automation was first successfully applied to semiconductor design verification. Mark graduated from MIT with a BS in EE&CS.
Ram Narayan is a Consulting Member of Technical Staff in Oracle Labs. He is a member of the RAPID Hardware Verification Team since January 2013. Prior to joining Oracle, Ram was a Principal Member of Technical Staff in the Platform Emulation Team at Advanced Micro Devices. In this capacity, he was driving improvements to the pre-silicon emulation strategy to impact the post-silicon validation effort and reduce the time to market. Ram joined AMD from Mentor Graphics in 2010. As an Application Engineer at Mentor Graphics, he helped Mentor's customers realize their verification goals with a range of technologies including Simulation, Formal Verification, Assertion and Coverage Based Verification, Testbench Automation, Hardware Software Co-verification and Hardware Emulation. Prior to joining Mentor Graphics, Ram was a Design Engineer in the K5 and K7 microprocessor design teams at AMD from 1993. His responsibilities included Architecure, RTL Design, Verification, Microcode Development and Hardware Emulation. Ram has 26 patents granted in the US. Ram received a B.Tech. in Electrical Engineering at The Indian Institute of Technology, Bombay in 1991 and an M.S. in Computer Engineering at The University of Texas at Austin in 1994.
Tom Fitzpatrick is currently a Verification Technologist at Mentor Graphics Corp. where he brings over two decades of design and verification experience to bear on developing advanced verification methodologies, particularly using SystemVerilog, and educating users on how to adopt them. He has been actively involved in the standardization of SystemVerilog, starting with his days as a member of the Superlog language design team at Co-Design Automation through its standardization via Accellera and then the IEEE, where he has served as chair of the 1364 Verilog Working Group, as well as a Technical Champion on the SystemVerilog P1800 Working Group. At Mentor Graphics, Tom was one of the original designers of the Advanced Verification Methodology (AVM), and later the Open Verification Methodology (OVM), and is the editor of Verification Horizons, a quarterly newsletter with approximately 40,000 subscribers. He is a charter member and key contributor to the Accellera Verification IP Technical Subcommittee. He has published multiple articles and technical papers about SystemVerilog, verification methodologies, assertion-based verification, functional coverage, formal verification and other functional verification topics.
Vigyan Singhal is the CEO of Oski Technology, a services company focussed on formal verification. Vigyan has practised formal verification since 1993. Previously he founded two startups, Jasper Design Automation and Elastix. He has a PhD from UC Berkeley, and BTech from IIT Kanpur.
Ahmed Eisawy is a member of the Technical & Product Marketing team ofthe Analog/Mixed-Signal group - part of the Deep Sub-micron Division - at Mentor Graphics. He's the product marketing manager for Kronos, the Cell Library Characterization and Validation, as well as Artist Link, the integration of the Mentor A/MS simulators into Cadence Virtuoso Analog Design Environment. For the last six years, he's been working as a member of the marketing team to drive the development of Analog/Mixed-Signal simulators forward with new technologies as well as engage with customers for evaluations, training & education, solving complex problems as well as help the customers through methodology assessments to improve their flow. Previously, Ahmed worked for six years in technical support where he worked closely with customers, helping resolve problems and help formulate the customer needs into tool enhancements. He received his BSEE from Cairo University in 1999 and his MSEE from the same university in 2002.
Linda Fosler is a seasoned professional providing marketing and operations management expertise for a diverse group of technologies and industries including computer systems, semiconductors, embedded systems and software and hardware design and verification tools. Linda is currently the director of marketing for the deep submicron (DSM) division of Mentor Graphics. Prior to this Linda was Vice President of Marketing and Business Development for VaST Systems, Esterel Technologies and IKOS Systems, as well as Vice President of Software Quality at Cadence Design Systems. Past accomplishments also include working as an independent consultant for a host of electronics related clients.
