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Experts at the Mentor Graphics Booth

We’ve brought some of our best researchers and partners to DAC just to meet you. Find your favorites in the list below. Then hurry and sign up for their sessions, before they fill up!

Featured Experts @ the Booth Events

Get Your FPGA Out of the Lab and into Production Monday, June 2, 9:00 AM

Technical Session Spending too much time in the Lab debugging your FPGA? FPGA’s have grown large and complex. So, too has the task of validating the functionality after it has passed all the tests for area, performance, and power. If there is a problem with your FPGA, where do you start looking? Combined with the powerful capabilities of the Mentor FPGA design flow spanning from design capture, implementation, and board design, come join us as we introduce new methods to not only produce better quality FPGA designs but also new methods and tools to help you instrument your FPGA design so that problems are easier to find as they happen.

A New Era in Functional Verification Monday, June 2, 10:00 AM

Technical Session This special Verification Academy DAC session presents a historical perspective of functional verification—from transistors to systems. And then discusses a new era in functional verification with the emergence of functional verification solutions that address today’s unique SoC challenges.

Full SoC Emulation from Device Drivers to Peripheral Interfaces Monday, June 2, 10:00 AM

Technical Session Companies have added a tape out requirement that ensures their SoC executes the OS loader to a boot prompt. Thus, verification of HW/SW interactions is no longer just a good idea, it’s a hard requirement. The methods for executing and debugging OS boot and device driver software on hardware during emulation are evolving rapidly. This session contrasts live versus off-line SW debug tools in the context of multi-core SoC designs, and physical versus virtual peripheral models as device driver targets. Participants will come away with an understanding of how an emulation-based, end-to-end flow yields a higher confidence at tape out and a faster time to market.

UVM Transactions - Important Undocumented Details Monday, June 2, 2:00 PM

Technical Session Fundamental questions most novice UVM users ponder include: Why uses classes instead of structs to define transactions for verification environments? What are advantages of using classes to represent transactions in a verification environment? Do I have to define different input and output classes for UVM testbenches? Why do I have to use do_methods() or field macros to override standard transaction methods? Why don't I just override the transaction methods directly? How do do_methods() and field macros work? SystemVerilog Guru and UVM expert, Cliff Cummings, will answer these questions and more to clarify many important details about UVM transactions.

Back to the Future: Is There Success without Moore's Law? Monday, June 2, 4:00 PM

Panel There seems to be a lot of angst in the industry over the increasing costs of extending IC scalability. For decades, the success of our industry has been predicated on Moore’s Law—the ability to deliver exponentially increasing logic density at continuously decreasing costs. Can the industry be successful without this virtuous cycle? The reality is that many players are doing very well without pushing the leading edge of scalability. This panel will look at the ways that IC innovators are adding value to established IC nodes through increasing functionality, reduced power consumption, higher reliability, integration of MEMS and silicon photonics, and die stacking. Come and pick up some new ideas from our panel while you’re enjoying Happy Hour at the Mentor booth.

100% Verified But the Chip Failed – Why? Monday, June 2, 4:00 PM

Technical Session You reached 100% coverage on your chip so why did it still fail? The problem may lie within your design process. Design flaws found late in the design cycle or, even worse, in the field or production, are not only costly, but could pose safety risks.  Mentor’s solution starts at the beginning – with the design requirements. Not verifying to the requirements can result in untested or incorrectly implemented aspects of the design. This session walks you through a repeatable requirements validation approach to verify 100% to the requirements.

How off-the-shelf IP can cut time spent on PCIe verification in half Tuesday, June 3, 9:00 AM

Technical Session The presentation will highlight how PLDA, built a PCIe UVM/SystemVerilog-based verification environment and how the work reduced time spent on verification by a factor of two compared to PLDA’s previous Verilog/SystemVerilog-based environment.

Achieving Broad & Flexible Debug Visibility if FPGA Prototypes Tuesday, June 3, 2:30 PM

Technical Session A key challenge in using FPGA prototypes is debugging, specifically in hardware or the interaction of software and hardware. Although many organizations have developed homegrown hardware instruments, silicon debug visibility continues to challenge the productive use of FPGA prototypes as a verification engine. Debugging system-level interactions driven by software sequences requires the ability to capture traces over a long period of time.This sessions discusses a solution that combines resource-efficient embedded instruments that dramatically increase visibility with software to provide a very flexible, easy-to-use silicon debug solution.

What will Moore's Law Cost Us at 10nm? Tuesday, June 3, 4:00 PM

Panel For the first time in many years, there is a lot of uncertainty about how we get to the next IC scaling nodes. Will EUV be ready? Will we have to go to triple or quadruple patterning? Can DSA be commercialized quickly enough? What are the cost implications for these various alternatives? Can we see a way to get to 10nm and 7nm with an affordable technology? Are we at the point where designs are so tightly linked to a manufacturer’s specific process that multi-sourcing is unfeasible? How much commonality is there, and what can tools do to hide the differences? If it’s doable, is multi-sourcing economically viable? This panel will consider these all important questions and provide some insights if not the final answers. Be prepared for a wide open discussion and some big differences of opinion. Come and get engaged in the discussion while you’re enjoying Happy Hour at the Mentor booth.

Formal Verification Signoff Methodology Wednesday, June 4, 11:00 AM

Technical Session Formal sign-off is a relatively new concept in the industry. Like simulation sign-off, it requires a thorough and systematic methodology. This includes: end-to-end checkers, constraints, abstraction models and coverage points. This talk discusses each component of the formal sign-off methodology so that formal can be applied in the verification sign-off flow to maximize efficiency & productivity.

Tackling FinFET Analog Mixed Signal and Memory Verification Wednesday, June 4, 4:00 PM

Panel Analog, mixed-signal, and SRAM design teams migrating to FinFET process nodes are implementing new architectures to take advantage of FinFET benefits and overcome its limitations. As a result they need to retool their transistor-level verification flow for more accuracy, performance and capacity to offset the increased layout, device modeling, device noise, voltage scaling, and process variation effects. Designers of complex analog/mixed-signal circuits such as PLLs, ADCs, SerDes, and transceivers, need to explore alternative architectures and measure their impact in non-planar silicon. Embedded SRAM design teams realize that it is no longer acceptable to tolerate 5% or more inaccuracy in memory IP characterization. This panel is an interactive forum where attendees can exchange ideas and questions with a group of experts who are tackling the exciting opportunities and challenges related to the move to FinFET nodes.

F = Full registration required

IC Design & Test

Arvind Narayanan, Product Marketing Manager, Integrated Circuit Implementation Division, Mentor Graphics

  • Mentor RTL to GDS Digital Implementation for Best PPA at Advanced Nodes
    Toggle Abstract

    TECHNICAL SESSION Achieving best power, performance and area (PPA) has gotten significantly more difficult at advanced nodes (20/16nm and below) due to inherent challenges . At smaller nodes the traditional design closure flow is inadequate due to complex DRC and DFM rules, multi-patterning (MP) and FinFET requirements, growing design sizes, low power requirements, high performance targets and increasing process and design variations. This session will highlight some of the advanced Oasys RealTime Designer(tm) and Olympus-SoC(tm) technologies to achieve best PPA and efficient RTL-to-GDS design closure. We will focus on unique technologies such as MP and FinFET aware implementation, high capacity RTL synthesis, RTL floorplanning, concurrent PPA optimization for best QoR, and DRC/DP signoff during implementation.

Carey Robertson, Director of Product Marketing, LVS and Extraction, Mentor Graphics

  • Parasitic Extraction to Meet the Challenge of Advanced Nodes
    Toggle Abstract

    TECHNICAL SESSION The world is 3D! Leading edge designers are considering new designs at advanced process nodes with 3D transistors (FinFETs). Others are considering “More than Moore” and opting for a 3D-IC approach. Everyone wants more accuracy which implies 3D modeling techniques to achieve high correlation against reference results. With these new challenges come traditional concerns of turn-around time (TAT), growing design complexity, double-patterning and growing number of interconnect corners that add to the challenge of robust parasitic extraction. This session will describe how new methods in Calibre have been developed to address these challenges and meet the performance, accuracy, and usability concerns for designers at all nodes.

Christen Decoin, Product Marketing Manager for New and Emerging Markets, Mentor Graphics

  • The Challenges of Power Grid Design in Advanced ICs
    Toggle Abstract

    TECHNICAL SESSION Power analysis has assumed a much more important and demanding role in the IC design flow. Exploding design sizes and complexity combined with a host of new analysis requirements has made this a very challenging design task. Designers need to analyze the impact of IR drop and current in-rush on signal integrity, current density and electro-migration impact on reliability, and other power-related issues. This session will review current issues with power analysis and discuss the capabilities needed to address them.

Jean-Marie Brunet, Product Marketing Director for Design for Manufacturing (DFM) and Place & Route Integration, Mentor Graphics

  • Samsung Ecosystem Collaboration with Mentor for DFM at 14nm and Below
    Toggle Abstract

    TECHNICAL SESSION For the 14nm node, Mentor and Samsung have collaborated extensively to create a comprehensive DFM solution that includes proven solutions for litho simulation, pattern matching, critical area analysis (CAA) and advanced filling. Come to this session to understand what was done and how it can help you move to 14nm.

Jeff Wilson, DFM Product Marketing Manager, Mentor Graphics

  • Update on DFM and Fill for Advanced Nodes
    Toggle Abstract

    TECHNICAL SESSION At 28 nm and below, litho process checking (LPC), CMP analysis and critical area analysis (CAA) are all crucial steps to help ensure manufacturability. In addition, layout fill has become a more complex and critical issue. Come to this session to understand today’s DFM issues, to find out what is required by the foundries at each node, to learn about updates to DFM tools, and to see how SmartFill is changing the approach to fill at advanced nodes.

Joe Kwan, Foundries Program Manager, Mentor Graphics

  • Update on DFM and Fill for Advanced Nodes
    Toggle Abstract

    TECHNICAL SESSION At 28 nm and below, litho process checking (LPC), CMP analysis and critical area analysis (CAA) are all crucial steps to help ensure manufacturability. In addition, layout fill has become a more complex and critical issue. Come to this session to understand today’s DFM issues, to find out what is required by the foundries at each node, to learn about updates to DFM tools, and to see how SmartFill is changing the approach to fill at advanced nodes.

Joe Sawicki, Vice President and General Manager Design to Silicon Division, Mentor Graphics

  • What will Moore's Law Cost Us at 10nm?
    Toggle Abstract

    PANEL For the first time in many years, there is a lot of uncertainty about how we get to the next IC scaling nodes. Will EUV be ready? Will we have to go to triple or quadruple patterning? Can DSA be commercialized quickly enough? What are the cost implications for these various alternatives? Can we see a way to get to 10nm and 7nm with an affordable technology? Are we at the point where designs are so tightly linked to a manufacturer’s specific process that multi-sourcing is unfeasible? How much commonality is there, and what can tools do to hide the differences? If it’s doable, is multi-sourcing economically viable? This panel will consider these all important questions and provide some insights if not the final answers. Be prepared for a wide open discussion and some big differences of opinion. Come and get engaged in the discussion while you’re enjoying Happy Hour at the Mentor booth.

John Ferguson, Director of Marketing, Calibre DRC Applications, Mentor Graphics

  • Not Jumping to 16/14nm Tomorrow? Extend the Lifetime and Get the Most Out of Established Nodes with Advanced Calibre
    Toggle Abstract

    TECHNICAL SESSION With the costs and complexity of 20nm and below, customers are staying longer at established nodes (e.g. 90nm – 28nm). They are also pushing much more complex designs through these nodes than ever before. Come learn how Calibre has solutions to help you get the most out of established processes for your next design.

Kalyan Chakravarthy, Member of Technical Staff, AMD

  • Better Layout in Less Time: AMD’s Experience with Calibre RealTime at 20nm and Below
    Toggle Abstract

    TECHNICAL SESSION Physical implementation is significantly more challenging at 20nm than at previous nodes. Introducing Calibre RealTime into the production flow at AMD enabled designers to meet this challenge and improve the quality of the layout at the same time. Calibre RealTime provides immediate feedback for implementation and the ability to optimize the layout with full sign-off feedback. This enables us to make last-minute edits with sign-off confidence, and to reduce the number of batch DRC iterations required to reach tape-out.

Kuang-Kuo Lin, Director of Foundry Design Enablement at America Headquarters Device Solutions, Samsung Semiconductor

  • Samsung Ecosystem Collaboration with Mentor for DFM at 14nm and Below
    Toggle Abstract

    TECHNICAL SESSION For the 14nm node, Mentor and Samsung have collaborated extensively to create a comprehensive DFM solution that includes proven solutions for litho simulation, pattern matching, critical area analysis (CAA) and advanced filling. Come to this session to understand what was done and how it can help you move to 14nm.

Marko Chew, Technical Marketing Engineer, Mentor Graphics

  • The Challenges of Power Grid Design in Advanced ICs
    Toggle Abstract

    TECHNICAL SESSION Power analysis has assumed a much more important and demanding role in the IC design flow. Exploding design sizes and complexity combined with a host of new analysis requirements has made this a very challenging design task. Designers need to analyze the impact of IR drop and current in-rush on signal integrity, current density and electro-migration impact on reliability, and other power-related issues. This session will review current issues with power analysis and discuss the capabilities needed to address them.

Matt Hogan, Product Marketing Manager, Calibre Design Solutions, Mentor Graphics

  • Improving Circuit Reliability with Calibre PERC
    Toggle Abstract

    TECHNICAL SESSION Circuit reliability continues to be a focus for all process nodes. Verification techniques that extend beyond traditional DRC, LVS and ERC checks are needed to meet the demands of today’s designs. Device and interconnect reliability solutions that are scalable across many designs without the need for manual intervention improves the repeatability and efficiency of these checks. Come see how we leverage unique technology with foundry-provided rule decks to solve some of the most challenging reliability concerns IC designers face. We will also discuss electrical overstress (EOS), current density and electromigration issues, to name a few, which can be solved by the comprehensive Calibre PERC reliability verification platform.

Michael Buehler-Garcia, Senior Director of Marketing for Calibre Design Solutions, Mentor Graphics

  • Back to the Future: Is There Success without Moore's Law?
    Toggle Abstract

    PANEL There seems to be a lot of angst in the industry over the increasing costs of extending IC scalability. For decades, the success of our industry has been predicated on Moore’s Law—the ability to deliver exponentially increasing logic density at continuously decreasing costs. Can the industry be successful without this virtuous cycle? The reality is that many players are doing very well without pushing the leading edge of scalability. This panel will look at the ways that IC innovators are adding value to established IC nodes through increasing functionality, reduced power consumption, higher reliability, integration of MEMS and silicon photonics, and die stacking. Come and pick up some new ideas from our panel while you’re enjoying Happy Hour at the Mentor booth.

Michael White, Director of Product Marketing, Calibre Physical Verification Products, Mentor Graphics

  • Calibre Advanced Physical Verification: Learn What’s Coming Your Way at 16/14nm and 10nm and How Calibre is Already Prepared
    Toggle Abstract

    TECHNICAL SESSION Physical verification (PV) complexity continues to grow by leaps and bounds as customers move to the advanced nodes that require multi-patterning and more recently FinFETs. Come learn about the emerging trends in PV and how the Calibre nmPlatform continues to rapidly expand, addressing the needs for advanced PV and helping you get your design to market faster.

Shankar Vellanthurai, Senior Product Engineer, Mentor Graphics

  • Mentor RTL to GDS Digital Implementation for Best PPA at Advanced Nodes
    Toggle Abstract

    TECHNICAL SESSION Achieving best power, performance and area (PPA) has gotten significantly more difficult at advanced nodes (20/16nm and below) due to inherent challenges . At smaller nodes the traditional design closure flow is inadequate due to complex DRC and DFM rules, multi-patterning (MP) and FinFET requirements, growing design sizes, low power requirements, high performance targets and increasing process and design variations. This session will highlight some of the advanced Oasys RealTime Designer(tm) and Olympus-SoC(tm) technologies to achieve best PPA and efficient RTL-to-GDS design closure. We will focus on unique technologies such as MP and FinFET aware implementation, high capacity RTL synthesis, RTL floorplanning, concurrent PPA optimization for best QoR, and DRC/DP signoff during implementation.

Srinivas Velivala, Calibre TME, Mentor Graphics

  • Better Layout in Less Time: AMD’s Experience with Calibre RealTime at 20nm and Below
    Toggle Abstract

    TECHNICAL SESSION Physical implementation is significantly more challenging at 20nm than at previous nodes. Introducing Calibre RealTime into the production flow at AMD enabled designers to meet this challenge and improve the quality of the layout at the same time. Calibre RealTime provides immediate feedback for implementation and the ability to optimize the layout with full sign-off feedback. This enables us to make last-minute edits with sign-off confidence, and to reduce the number of batch DRC iterations required to reach tape-out.

Steve Pateras, Product Marketing Director, Silicon Test Products, Mentor Graphics

  • Test Solutions for High-Quality Automotive Devices
    Toggle Abstract

    TECHNICAL SESSION The growing amount of electronics within today’s automobiles is driving very high quality and reliability requirements to a widening range of semiconductor devices. Improvements in test solutions are needed not only to maintain very high quality levels in more advanced technology nodes but to also address increasing reliability requirements such as defined within the ISO 26262 standard. New test approaches to be described will include a new hybrid ATPG compression and logic BIST solution that provides more efficient defect coverage together with the ability to apply tests within the system for long-term reliability. This hybrid solution also supports a new cell-aware test generation approach that has been shown to significantly reduce DPM levels in shipped devices.

Design & Functional Verification

Anissa Mawer, Verification Technology Manager, Mentor Graphics

  • Visualizer: A Powerful Debug Environment for Complex SOCs
    Toggle Abstract

    TECHNICAL SESSION This session will focus on improving debug productivity with Visualizer, Mentor’s NEW high performance and capacity debug environment. Visualizer is tightly integrated with both Questa simulation and Veloce emulation to improve debug productivity for RTL, gates and SV/UVM testbenches. Visualizer is fast and intuitive with powerful, automated features that help pinpoint the cause of errors and explore your design.

Jim Kenney, Marketing Director, Mentor Graphics

  • Get Your FPGA Out of the Lab and into Production
    Toggle Abstract

    TECHNICAL SESSION Spending too much time in the Lab debugging your FPGA? FPGA’s have grown large and complex. So, too has the task of validating the functionality after it has passed all the tests for area, performance, and power. If there is a problem with your FPGA, where do you start looking? Combined with the powerful capabilities of the Mentor FPGA design flow spanning from design capture, implementation, and board design, come join us as we introduce new methods to not only produce better quality FPGA designs but also new methods and tools to help you instrument your FPGA design so that problems are easier to find as they happen.

Roger Sabbagh, Product Marketing Manager, Mentor Graphics

  • How to Accelerate Verification with 5 Easy to Use Formal Apps
    Toggle Abstract

    TECHNICAL SESSION What if you could harness the benefits of formal verification without the pain? That’s exactly what Questa’s fully-automatic formal apps allow you to do. This session presents the top 5 apps used to get better quality designs out the door faster. We’ll review apps for: (1) Clock-domain crossings, (2) Common RTL coding errors, (3) X-states, (4) Coverage closure, (5) Property generation.

Shabtay Matalon, Market Development Manager, Mentor Graphics

  • Innovative Virtual Prototype Technologies for System and Application Bring-up
    Toggle Abstract

    TECHNICAL SESSION Traditional embedded system design is transforming to a new world of Virtual embedded software and hardware design. Mentor’s virtual prototyping solution is revolutionizing embedded platform-based design by enabling debug of hardware/software complex interactions and by providing analysis capabilities not achievable with traditional simulation or on prototyping boards. It offers a tightly coupled HW/SW debug, analysis and verification capabilities that are changing the traditional design paradigm on prototyping boards. This includes observing the behaviour of the platform’s software in a non-intrusive manner, without introducing any observation effects. This session will illustrate the level of control, visibility and analysis capabilities available on a reference virtual prototype to guide efficient software and hardware development that meets the functionality and performance goals.

Steve Bailey, Director of Emerging Technologies, Mentor Graphics

  • Questa: High-Performance Simulation, Emulation and much more
    Toggle Abstract

    TECHNICAL SESSION With the growing size, complexity and software content of today’s SoC designs, verification requires a platform that gives you more than just simulation. Come see how Questa ties simulation, formal and emulation together and brings testbench automation, coverage closure, low power, abstract portable stimulus, new system-level metrics and more to maximizes your verification productivity.

Valerie Rachko, Marketing Director, Mentor Graphics

  • 100% Verified But the Chip Failed – Why?
    Toggle Abstract

    TECHNICAL SESSION You reached 100% coverage on your chip so why did it still fail? The problem may lie within your design process. Design flaws found late in the design cycle or, even worse, in the field or production, are not only costly, but could pose safety risks.  Mentor’s solution starts at the beginning – with the design requirements. Not verifying to the requirements can result in untested or incorrectly implemented aspects of the design. This session walks you through a repeatable requirements validation approach to verify 100% to the requirements.

Verification Academy

Anand Iyer, Product Marketing, Calypto

  • Power exploration to RTL power convergence for advanced designs
    Toggle Abstract

    TECHNICAL SESSION Because over 80% of the final SoC/IP power is decided at the RT level, designers need to explore multiple power intent options and converge on power goals prior to place and route.  This presentation will discuss how Questa-Power Aware and Calypto PowerPro enables users to accurately analyze various power intent choices and then optimize for best power reduction at RTL without losing any functionality.

Cliff Cummings, President, Sunburst Design

  • UVM Transactions - Important Undocumented Details
    Toggle Abstract

    TECHNICAL SESSION Fundamental questions most novice UVM users ponder include: Why uses classes instead of structs to define transactions for verification environments? What are advantages of using classes to represent transactions in a verification environment? Do I have to define different input and output classes for UVM testbenches? Why do I have to use do_methods() or field macros to override standard transaction methods? Why don't I just override the transaction methods directly? How do do_methods() and field macros work? SystemVerilog Guru and UVM expert, Cliff Cummings, will answer these questions and more to clarify many important details about UVM transactions.

Harry Foster, Chief Verification Scientist, Mentor Graphics

  • A New Era in Functional Verification
    Toggle Abstract

    TECHNICAL SESSION This special Verification Academy DAC session presents a historical perspective of functional verification—from transistors to systems. And then discusses a new era in functional verification with the emergence of functional verification solutions that address today’s unique SoC challenges.

Jeremy Levitt, Engineering Manager, Mentor Graphics

  • Instant Formal Expert
    Toggle Abstract

    TECHNICAL SESSION Formal sign-off is a relatively new concept in the industry. Like simulation sign-off, it requires a thorough and systematic methodology. This includes: end-to-end checkers, constraints, abstraction models and coverage points. This talk discusses each component of the formal sign-off methodology so that formal can be applied in the verification sign-off flow to maximize efficiency & productivity.

Matthew Balance, Verification Technologist, Mentor Graphics

  • Maximize Verification Reuse with Portable Stimulus
    Toggle Abstract

    TECHNICAL SESSION Verification productivity and reuse are of key concern when verifying today’s complex designs. The ability to rapidly create large amounts of comprehensive test sequences at block, subsystem, SoC and system level are key to ensuring design quality. One key obstacle to achieving comprehensive testing today is the lack of a consistent stimulus specification that is reusable from block to system level. Recently, in response to industry demand, the Accellera Systems Initiative board launched a proposed working group to investigate whether to standardize a portable stimulus specification. This session will show how a portable stimulus specification brings 10-100x faster coverage closure to block level verification, and reusable comprehensive tests to SoC and system level verification

Rich Edelman, Verification Architect, Mentor Graphics

  • Verification and Debug: Old School Meets New School
    Toggle Abstract

    TECHNICAL SESSION “Old school” debug typically involves applying vectors directly to the design, a level of self-checking and then exploring the design with source, waves, and others to figure out what went wrong. With “new school” verification methodologies (UVM, randomization, golden reference models) the debug techniques need to be expanded. This session covers how you use the best of both worlds to find problems faster and to better answer “if you are done yet”.

Romain Tourneau, PLDA

  • How off-the-shelf IP can cut time spent on PCIe verification in half
    Toggle Abstract

    TECHNICAL SESSION The presentation will highlight how PLDA, built a PCIe UVM/SystemVerilog-based verification environment and how the work reduced time spent on verification by a factor of two compared to PLDA’s previous Verilog/SystemVerilog-based environment.

Steve Bailey, Director of Emerging Technologies, Mentor Graphics

  • Achieving Broad & Flexible Debug Visibility if FPGA Prototypes
    Toggle Abstract

    TECHNICAL SESSION A key challenge in using FPGA prototypes is debugging, specifically in hardware or the interaction of software and hardware. Although many organizations have developed homegrown hardware instruments, silicon debug visibility continues to challenge the productive use of FPGA prototypes as a verification engine. Debugging system-level interactions driven by software sequences requires the ability to capture traces over a long period of time.This sessions discusses a solution that combines resource-efficient embedded instruments that dramatically increase visibility with software to provide a very flexible, easy-to-use silicon debug solution.

Tom Fitzpatrick, Verification Technologist, Mentor Graphics

  • UVM: What’s New, What’s Next, and Why You Care
    Toggle Abstract

    TECHNICAL SESSION You may have heard there’s a new version of UVM that’s recently been released. This session will teach you everything you need to know about the future of UVM. We’ll briefly cover the new features included in UVM1.2 and how to minimize their impact, and we’ll identify the key subset of UVM features that will make your environment truly reusable from block to system-level verification while providing the ideal platform for integrating new solutions and standards.

Vigyan Singhal, President and CEO, Oski

  • Formal Verification Signoff Methodology
    Toggle Abstract

    TECHNICAL SESSION Formal sign-off is a relatively new concept in the industry. Like simulation sign-off, it requires a thorough and systematic methodology. This includes: end-to-end checkers, constraints, abstraction models and coverage points. This talk discusses each component of the formal sign-off methodology so that formal can be applied in the verification sign-off flow to maximize efficiency & productivity.

AMS/Custom IC Design

Mick Tegethoff, Product Marketing Manager, Mentor Graphics

  • Introduction to the Analog FastSPICE (AFS) Platform
    Toggle Abstract

    TECHNICAL SESSION The latest addition to the Mentor analog/mixed-signal simulation and verification family is the Analog FastSPICE (AFS) Platform developed by Berkeley Design Automation (BDA), now part of Mentor. This session provides details on the AFS Platform, the world’s fastest circuit verification for nanometer analog, RF, mixed-signal, and custom digital circuits. Foundry certified to 16nm/14nm FinFET-based processes, the AFS Platform delivers nanometer SPICE accuracy 5x-10x faster than traditional SPICE and 2x-6x faster than parallel SPICE simulators. For large analog/mixed-signal circuits, the AFS Platform delivers greater than 10M-element capacity and the fastest mixed-signal simulation. For silicon-accurate characterization, it includes the industry’s only full-spectrum, device noise analysis and delivers near-linear performance scaling with the number of cores. Come hear what Analog FastSPICE can do for your analog/mixed-signal design and verification flow.

Ravi Subramanian, General Manager, AMS, Mentor Graphics

  • Tackling FinFET Analog Mixed Signal and Memory Verification
    Toggle Abstract

    PANEL Analog, mixed-signal, and SRAM design teams migrating to FinFET process nodes are implementing new architectures to take advantage of FinFET benefits and overcome its limitations. As a result they need to retool their transistor-level verification flow for more accuracy, performance and capacity to offset the increased layout, device modeling, device noise, voltage scaling, and process variation effects. Designers of complex analog/mixed-signal circuits such as PLLs, ADCs, SerDes, and transceivers, need to explore alternative architectures and measure their impact in non-planar silicon. Embedded SRAM design teams realize that it is no longer acceptable to tolerate 5% or more inaccuracy in memory IP characterization. This panel is an interactive forum where attendees can exchange ideas and questions with a group of experts who are tackling the exciting opportunities and challenges related to the move to FinFET nodes.

Tom Daspit, Product Marketing Manager, Mentor Graphics

  • Custom IC Design and AMS Simulation/Verification – Unparalleled Insight and Productivity
    Toggle Abstract

    TECHNICAL SESSION From our complete Custom IC Design flow through our industry leading simulators and analog/ mixed-signal verification systems, Mentor solutions provide insight and productivity.  This session provides an overview of the analog/mixed-signal product portfolio with an emphasis on new capabilities, recent customer results, and a future vision.  We introduce the newest member of the portfolio, the Analog FastSPICE Platform from Berkeley Design Automation (BDA), now part of Mentor.