Home Technical Events DAC 2013 Mentor Experts in the DAC Conference

Mentor Experts in the DAC Conference

Come listen to our brightest researchers and executives discuss the latest design issues in the DAC Conference panels, tutorials, workshops, papers and in the user track.

F = Full DAC registration required

IC Design & Test

Juan Rey, Sr. Director of Engineering, Mentor Graphics

Juan C. Rey is the Senior Engineering Director for the Calibre product line in the Design to Silicon Division at Mentor Graphics Corporation. His group is responsible for the architecture, design and development of Mentor’s software product line for integrated circuit physical verification and tape out tasks such as design rule checking, layout vs. schematic verification, capacitance, resistance and inductance extraction, resolution enhancement, mask data preparation and design for manufacturing. Juan has 30 years of software development experience ranging from research activities at Stanford University (EE department), to development and management of electronic design automation and process and device modeling software at Technology Modeling Associates, Cadence and Mentor Graphics. Juan also represents his company at the Executive Technology Advisory Board of Semiconductor Research Corporation (SRC) and is responsible for the IP portfolio and research initiatives of his division.

Will Data Explosion Blow Up the IC Design Flow? F Abstract

PANEL The sheer volume of information needed to capture, model, verify, manufacture, and test an SoC is exploding. Challenges include increasing runtimes, data center costs, and sharing information securely across multiple locations. Learn about possible solutions: new design methodologies, cloud services, secure ecosystem networks, and more efficient data formats.

Valeriy Sukharev, Principle Engineer, Mentor Graphics

Valeriy Sukharev is the Technical Lead and Principle Engineer of the Design-to-Silicon division of Mentor Graphics Corporation. Dr. Sukharev leads research and development of new full-chip modeling and simulation capabilities for the semiconductor processing and DFM/DFR applications. He has authored and edited a number of books, published more than 100 papers in scientific journals and holds 20 plus U.S. patents. He has been with Mentor Graphics R&D for five years. Prior to Mentor Graphics, Dr. Sukharev was a Visiting Professor with Brown University, Providence, RI, and a Guest Researcher with the National Institute of Standards and Technology (NIST), Gaithersburg, MD. He held senior technical positions at LSI Logic Advanced Development Lab, Milpitas, CA. He holds Ph.D. in physical chemistry from the Karpov Institute of Physical Chemistry, Moscow, Russia.

Advanced Node Reliability: Are We in Trouble? F Abstract

PANEL As designs move to 20nm and 14nm, reliability issues have become increasingly complex. EM is now a critical design sign-off requirement. ESD failures can significantly degrade the yield. Wear out-related defects impact circuit margining and lifetime requirement for critical applications. This panel will discuss the reliability challenges and debate what would be the best ways for designers, foundries, and EDA vendors to define and develop advanced circuit checks and design sign-off at these advanced nodes.

Design & Functional Verification

Atul Pandey, Application Engineer, Mentor Graphics

Atul Pandey is a European Product Specialist for Analog and Mixed Signal solutions. He is supporting customers on Mentor's AMS products and solutions. He joined Mentor Graphics in 2008.Atul has expertise in Analog and Digital Circuit Design and Verification .Prior to joining Mentor Graphics, He has worked with STMicroelectronics, Intel and Infineon/Qimonda between 2001 and 2008 as Analog circuit designer on variety of Analog circuit blocks and IPs. Atul holds a Masters Degree in Integrated Electronics and Circuits from Indian Institute of Technology, Delhi(India).

Coverage-Driven Verification for Analog Design Based on UCIS F Abstract

PRESENTATION Although front-end designers like to live in the ideal world presented by digital RTL modeling, many can no longer afford this luxury. It is increasingly important to include awareness of analog and other physical issues as early as possible in the design process. In this session we will hear about designer experiences with techniques that examine and verify analog and physical issues during the front-end phase of processor design.

Erich Marschner, Vice-chair of the IEEE P1801 UPF Working Group and Verification Architect, Mentor Graphics

Low-Power Design with the New IEEE 1801-2013 Standard F Abstract

WORKSHOP The workshop will cover an introduction to the low power design intent concepts and methodologies fundamental to IEEE 1801, as well as detailed discussion of the main changes from the previous version (IEEE 1801-2009). The workshop will concentrate on the standard, its underlying semantics and intended methodologies, illustrated by real world examples. The presenters are all members of the IEEE 1801 working group, and are technical experts on the subject.

Harry Foster, Chief Verification Scientist, Mentor Graphics

Harry Foster is Chief Scientist for Mentor Graphics' Design Verification Technology Division. He holds multiple patents in verification and has co-authored seven books on verification. Harry was the 2006 recipient of the Accellera Technical Excellence Award for his contributions in developing industry standards.

EDA: Meet Analytics; Analytics: Meet EDA F Abstract

PANEL The sheer scale of data generated by EDA tools used on an system-on-chip (SoC) suggest that analytics should play a major role in speedy SoC completion. This is especially true for Functional Verification where analytics can be helpful in sizing the problem, assessing progress, and improving process. However, beyond familiar coverage metrics, this is not the case today. This panel considers statistical analysis, data mining, machine learning, and other analytic methods to gain more insight into verification – and whether the analytics approach can extend to other SoC design areas.

Jon McDonald, Sr. Technical Marketing Engineer, Mentor Graphics

Jon McDonald is Sr. Technical Marketing Engineer at Mentor Graphics. He received a BS in Electrical and Computer Engineering from Carnegie Mellon and an MS in Computer Science from Polytechnic University. He has been active in digital design, language based design and architectural modeling for over 15 years. Prior to joining Mentor Graphics Mr. McDonald held senior technical engineering positions with Summit Design, Viewlogic Systems and HHB Systems.

Supercharge Your GPU F Abstract

WORKSHOP In this tutorial, we will present the evolution of an OpenGL ES application development and execution flow across software and hardware threads and through virtual and physical embedded hardware targets. The entire flow is driven with a unified native Software IDE with embedded hardware visibility and profiling features.

The tutorial will delve into all aspects of software-driven debugging and optimization while migrating from a pure virtual prototype target, and software rendering implementation across to graphical processing engine executing on an emulator or a physical board.

The real-world impact of the flow described in this tutorial is far reaching. Graphical applications such as visual computing, image processing and 3D animation and navigation are a fundamental component of many modern mobile, automotive and gaming devices.

Mark Olen, Functional Verification Technologist, Mentor Graphics

Mark Olen is currently a Functional Verification Technologist at Mentor Graphics Corp. He has spent over thirty years in semiconductor design verification and manufacturing test, and has authored papers in the areas of intelligent testbench automation, design for test technology, and semiconductor manufacturing test automation. He wrote his first testbench in 1981 at Raytheon, and went on to spend ten years working at Teradyne in the ATE and DFT industries. He became Vice President of Cascade Microtech's thin film wafer probe division, before co-founding Lighthouse Design Automation where graph-based Intelligent Testbench Automation was first successfully applied to semiconductor design verification. Mark graduated from MIT with a BS in EE&CS.

Fabric Verification Using an Advanced Graph-Based Solution F

AMS/Custom IC Design

Amr M. Tosson, Senior Technical Marketing Engineer for GRD Egypt Management, Mentor Graphics

Amr M. Tosson graduated with honors from the department of Electronics and Communications Engineering of Cairo University in 2006. He obtained his MSc in Electronics from the same department in 2009. In addition to pursuing a PhD degree from the University of Waterloo, Amr is a Sr. Software Development Engineer at Mentor Graphics

Pioneering an On-the-Fly Simulation Technique for the Detection of Layout-Dependent Effects During IC Design Phase F

Mentor Experts in the DAC Conference

IC Design & Test

Design & Functional Verification

Erich Marschner, Vice-chair of the IEEE P1801 UPF Working Group and Verification Architect, Mentor Graphics

AMS/Custom IC Design

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