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Mentor Experts in the DAC Conference

Come listen to our brightest researchers and executives discuss the latest design issues in the DAC Conference panels, tutorials, workshops, papers and in the user track.

Featured Experts @ the Conference Events

Is Model-Driven Development the Answer to Design Complexity? Wednesday, June 4, 4:00 PM

Panel The challenge of increased complexity in the development of next-generation embedded and cyberphysical systems is still to be solved. Many different solutions are being proposed, targeting a subset of multiple domains that must be integrated together depending on the starting design point, including physical, mathematical, digital, electronics and software. Different types of tools are competing on the market, all promising to solve the problem of modeling cyberphysical systems. Model-driven development, heterogeneous system modeling frameworks, prototyping frameworks: what is the best methodology?

F = Full registration required

IC Design & Test

Andres Torres, Product Lead Engineer, Mentor Graphics

  • Challenges in Applying Machine Learning Techniques and Data Mining in Physical Verification F
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    TECHNICAL SESSION Data mining is the process of extracting previously-unknown interesting patterns from large quantities of data. Data mining is particularly applicable to problems that involve discovering trends, anomalies and/or dependencies in the data. Many such problems occur in the context of EDA, e.g., in functional verification, timing analysis, physical verification, test, debug and diagnosis. This session begins with an overview of data mining techniques, the types of problems they solve and their potential applications in EDA. The introduction is followed by two talks that provide in-depth discussion in specific areas. The first focuses on test and functional verification. It overviews promising applications and shares experiences implementing a data-mining-based methodology in several industrial applications. The second focuses on physical verification and addresses practical applicability and limitations of data-mining using hot-spot detection as an example.

Armen Kteyan, Lead Engineer, Mentor Graphics

  • Stress Assessment for Device Performance in 3D IC F

Dina Medhat, Senior Technical Marketing Engineer, Mentor Graphics

  • Physical Verification of Hierarchical Analog Design Constraints for Automotive ICs F

Dusan Petranovic, Technical Marketing Engineer, Mentor Graphics

  • Fast and Accurate Full-chip Extraction and Optimization of TSV-to-Wire Coupling F
    Toggle Abstract

    TECHNICAL PAPER This session covers topics from transistor-level to circuit-level modeling in 2D and 3D IC designs.

Fedor Pikus, Chief Engineering Scientist, Mentor Graphics

  • Designing In Security: What Will It Take? F
    Toggle Abstract

    PANEL The security and trustworthiness of everything from large-scale servers in the cloud to the lock on a hotel room are of growing concern. With the proliferation of intelligent, networked devices and systems, the “hardware root of trust” is a vital component of overall security. A panel of industry experts will provide perspectives on the challenges to development and adoption of strategies and techniques for Designing In Security, and research that is needed to accelerate progress. A new industry consortium on Trustworthy and Secure Semiconductors and Systems (T3S) that is partnering with government to support fundamental research also will be discussed.

Gevorg Gevorgyan, Engineer, Mentor Graphics

  • Stress Assessment for Device Performance in 3D IC F

Grzegorz Mrugalski, SW Development Manager, Mentor Graphics

  • On Using Implied Values in EDT-Based Test Compression F
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    TECHNICAL PAPER If process variations, defects or test costs keep you up at night, this is your chance to face your demons. This session introduces novel test methods to uncover defects, diagnosis strategies to pinpoint failure root-cause and calibration techniques to compensate for manufacturing imperfections.

Hartmut Marquardt, Senior Application Engineer, Mentor Graphics

  • Physical Verification of Hierarchical Analog Design Constraints for Automotive ICs F

Henrik Hovsepyan, R&D Manager, Mentor Graphics

  • Stress Assessment for Device Performance in 3D IC F

Ivailo Nedelchev, Chief Technologist, Mentor Graphics

  • On Timing Closure: Buffer Insertion for Hold-Violation Removal F
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    TECHNICAL PAPER This session discusses some key challenges in timing closure and future generation physical design. The first two papers specifically discuss physical challenges of 3D ICs in terms of design methodologies, performance and packaging while the remaining papers present new techniques and algorithms for timing closure of high-performance designs.

Janusz Rajski, Development Engineer Director, Mentor Graphics

  • On Using Implied Values in EDT-Based Test Compression F
    Toggle Abstract

    TECHNICAL PAPER If process variations, defects or test costs keep you up at night, this is your chance to face your demons. This session introduces novel test methods to uncover defects, diagnosis strategies to pinpoint failure root-cause and calibration techniques to compensate for manufacturing imperfections.

Jean-Marie Brunet, Product Marketing Director for Design for Manufacturing (DFM) and Place & Route Integration, Mentor Graphics

  • FinFET and IC Design: Mountain or Mole Hill? F
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    PANEL FinFETs have moved from the industry roadmap into industry deployment. The test chips are back. Many designs are underway. The 14nm process is being projected to tighter rules that will bring even more concerns about FIN gate performance, depending on many factors such as sidewall and FIN characteristics, including pitches and height to mention some. The pressing questions from many are: how big of a deal are FinFETs to my design process? How is the EDA industry responding to design needs to predict the impact of the FIN parameters in device performance, reliability and manufacturability in general?

Jen Chen, Senior Application Engineer, Mentor Graphics

  • Advanced Layout Reliability Verification Methodology For Mixed Signal and Multi-Power Domain Designs F

Jun-Ho Choy, Engineer, Mentor Graphics

  • Stress Assessment for Device Performance in 3D IC F

Khaled Mohamed, Technical Engineer, Mentor Graphics

  • New Trends in TSV: SWCNT-Based TSV and Air-Gap Based Coaxial TSV F

Mohamed Dessouky, Engineer, Mentor Graphics

  • Modeling Proximity-Induced Variability in Standard Cells for Optimized Timing Performance F

Mohamed Said, Senior IC Design Consultant, Mentor Graphics

  • Modeling Proximity-Induced Variability in Standard Cells for Optimized Timing Performance F

Nilanjan Mukherjee, Development Engineer Director, Mentor Graphics

  • On Using Implied Values in EDT-Based Test Compression F
    Toggle Abstract

    TECHNICAL PAPER If process variations, defects or test costs keep you up at night, this is your chance to face your demons. This session introduces novel test methods to uncover defects, diagnosis strategies to pinpoint failure root-cause and calibration techniques to compensate for manufacturing imperfections.

Robert Todd, Chief Engineering Scientist, Mentor Graphics

  • Geometric Pattern Match Using Edge Driven Dissected Rectangles and Vector Space F

Sarvesh Bhardwaj, Lead Engineer, Mentor Graphics

  • On Timing Closure: Buffer Insertion for Hold-Violation Removal F
    Toggle Abstract

    TECHNICAL PAPER This session discusses some key challenges in timing closure and future generation physical design. The first two papers specifically discuss physical challenges of 3D ICs in terms of design methodologies, performance and packaging while the remaining papers present new techniques and algorithms for timing closure of high-performance designs.

Sridhar Srinivasan, R&D Staff Engineer, Mentor Graphics

  • Advanced Layout Reliability Verification Methodology For Mixed Signal and Multi-Power Domain Designs F

Srinivas Velivala, Calibre TME, Mentor Graphics

  • Advanced Layout Reliability Verification Methodology For Mixed Signal and Multi-Power Domain Designs F

Valeriy Sukharev, Principle Engineer, Mentor Graphics

  • Stress Assessment for Device Performance in 3D IC F

Vidyamani Parkhe, IC Architect, Mentor Graphics

  • On Timing Closure: Buffer Insertion for Hold-Violation Removal F
    Toggle Abstract

    TECHNICAL PAPER This session discusses some key challenges in timing closure and future generation physical design. The first two papers specifically discuss physical challenges of 3D ICs in terms of design methodologies, performance and packaging while the remaining papers present new techniques and algorithms for timing closure of high-performance designs.

Design & Functional Verification

Harry Foster, Chief Verification Scientist, Mentor Graphics

  • End-User Applications - Tests for Nothing and Verification for Free F
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    PANEL To verify an IP one can create new tests  or extract IP-level tests from existing application software. So far, verification teams have been creating new tests for each new IP. While highly efficient tests can be created , the process is time consuming. The alternative of test extraction is inefficient. But, what if the process of extracting IP-level tests from application software were automated?  A large trove of tests would be readily available even before a new IP development began. One camp believes that extraction  is an old idea: it never has worked because it is not efficient. Another camp believes that today this is possibly the only way to complete verification on time. Who holds the winning approach?

Roger Sabbagh, Product Marketing Manager, Mentor Graphics

  • Power Aware Clock Domain Crossing Verification F
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    TECHNICAL SESSION Formal and static methods, which analyze a design directly rather than depending on large numbers of simulation vectors, are becoming increasingly important in the world of modern design. In the first part of this session, real-world practitioners who have been successful with formal verification describe case studies and use them to supply useful advice for those who wish to achieve similar results. Then we move on to describe some new and powerful uses for static and formal techniques in conjunction with other tools and methods, providing new insights into IP integration, clock domain crossings, power issues, and clock/reset design.

Saumitra Goel, Lead Consultant Staff, Mentor Graphics

  • Power Aware Clock Domain Crossing Verification F
    Toggle Abstract

    TECHNICAL SESSION Formal and static methods, which analyze a design directly rather than depending on large numbers of simulation vectors, are becoming increasingly important in the world of modern design. In the first part of this session, real-world practitioners who have been successful with formal verification describe case studies and use them to supply useful advice for those who wish to achieve similar results. Then we move on to describe some new and powerful uses for static and formal techniques in conjunction with other tools and methods, providing new insights into IP integration, clock domain crossings, power issues, and clock/reset design.

Embedded Software

Serge Leef, VP New Ventures, GM System-Level Engineering Division, Mentor Graphics

  • Is Model-Driven Development the Answer to Design Complexity? F
    Toggle Abstract

    PANEL The challenge of increased complexity in the development of next-generation embedded and cyberphysical systems is still to be solved. Many different solutions are being proposed, targeting a subset of multiple domains that must be integrated together depending on the starting design point, including physical, mathematical, digital, electronics and software. Different types of tools are competing on the market, all promising to solve the problem of modeling cyberphysical systems. Model-driven development, heterogeneous system modeling frameworks, prototyping frameworks: what is the best methodology?

Automotive

Andrew Patterson, Director, Automotive, Mentor Graphics

  • Connected Engineering for Automtive EE Design F
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    TECHNICAL SESSION A well managed process with seamless information flow from concept to design to verification to in-production updating (e.g. software updates) is the holy grail for a fully enabled Systems Engineering process. Aspects of this enablement is the theme of this session and it looks at three different views of how systems engineering is enabled at various levels in the process.

Serge Leef, VP New Ventures, GM System-Level Engineering Division, Mentor Graphics

  • Applying EDA Techniques to Analysis and Optimization to In-vehicle Distributed Systems F
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    TECHNICAL SESSION Modern vehicles have complex architectures with many electronic control units (ECUs) and different communication buses that are used to implement different distributed control algorithms. Developing such complex hardware/software systems rely on building accurate virtual prototypes ad simulators, which are used both for systems design & optimization, as well as for parallel software development. This session will feature different talks discussing various challenges and solutions in this domain.

Walden Rhines, Chairman and Chief Executive Officer, Mentor Graphics

  • Fireside Chat: Automotive Engineers Love Design Automation
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    PANEL Having heard the exciting and informative keynote in the formal setting, come to the Pavilion for an informal interaction with James Buczkowski as Wally Rhines engages him in a wide ranging conversation from his career and cars of the future to designing for safety and the role of EDA in his world. Be prepared to ask your own questions such as why the nifty feature everyone wants in their car is missing, or if a driverless flying car will ever be available for the masses?