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Verification Academy

Be sure to visit the Verification Academy booth on the DAC exhibit floor where Mentor will be digging deeper into the challenges of IC Design and Verification with presentations and lively conversation.

Featured Verification Academy Events

A New Era in Functional Verification Monday, June 2, 10:00 AM

Technical Session This special Verification Academy DAC session presents a historical perspective of functional verification—from transistors to systems. And then discusses a new era in functional verification with the emergence of functional verification solutions that address today’s unique SoC challenges.

UVM Transactions - Important Undocumented Details Monday, June 2, 2:00 PM

Technical Session Fundamental questions most novice UVM users ponder include: Why uses classes instead of structs to define transactions for verification environments? What are advantages of using classes to represent transactions in a verification environment? Do I have to define different input and output classes for UVM testbenches? Why do I have to use do_methods() or field macros to override standard transaction methods? Why don't I just override the transaction methods directly? How do do_methods() and field macros work? SystemVerilog Guru and UVM expert, Cliff Cummings, will answer these questions and more to clarify many important details about UVM transactions.

How off-the-shelf IP can cut time spent on PCIe verification in half Tuesday, June 3, 9:00 AM

Technical Session The presentation will highlight how PLDA, built a PCIe UVM/SystemVerilog-based verification environment and how the work reduced time spent on verification by a factor of two compared to PLDA’s previous Verilog/SystemVerilog-based environment.

Achieving Broad & Flexible Debug Visibility if FPGA Prototypes Tuesday, June 3, 2:30 PM

Technical Session A key challenge in using FPGA prototypes is debugging, specifically in hardware or the interaction of software and hardware. Although many organizations have developed homegrown hardware instruments, silicon debug visibility continues to challenge the productive use of FPGA prototypes as a verification engine. Debugging system-level interactions driven by software sequences requires the ability to capture traces over a long period of time.This sessions discusses a solution that combines resource-efficient embedded instruments that dramatically increase visibility with software to provide a very flexible, easy-to-use silicon debug solution.

Formal Verification Signoff Methodology Wednesday, June 4, 11:00 AM

Technical Session Formal sign-off is a relatively new concept in the industry. Like simulation sign-off, it requires a thorough and systematic methodology. This includes: end-to-end checkers, constraints, abstraction models and coverage points. This talk discusses each component of the formal sign-off methodology so that formal can be applied in the verification sign-off flow to maximize efficiency & productivity.

F = Full registration required

Experts @ the Booth
  • A New Era in Functional Verification
    Toggle Abstract

    TECHNICAL SESSION This special Verification Academy DAC session presents a historical perspective of functional verification—from transistors to systems. And then discusses a new era in functional verification with the emergence of functional verification solutions that address today’s unique SoC challenges.

Presenter: Harry Foster, Chief Verification Scientist, Mentor Graphics
Products: Questa
  • Achieving Broad & Flexible Debug Visibility if FPGA Prototypes
    Toggle Abstract

    TECHNICAL SESSION A key challenge in using FPGA prototypes is debugging, specifically in hardware or the interaction of software and hardware. Although many organizations have developed homegrown hardware instruments, silicon debug visibility continues to challenge the productive use of FPGA prototypes as a verification engine. Debugging system-level interactions driven by software sequences requires the ability to capture traces over a long period of time.This sessions discusses a solution that combines resource-efficient embedded instruments that dramatically increase visibility with software to provide a very flexible, easy-to-use silicon debug solution.

Presenter: Steve Bailey, Director of Emerging Technologies, Mentor Graphics
Products: Questa
  • AMBA®CHI and the Mentor Enterprise Verification Platform
    Toggle Abstract

    TECHNICAL SESSION The complexity and size of fabrics based on AMBA® 5 CHI present new verification challenges. This presentation from ARM and Mentor Graphics gives a brief introduction to the CHI protocol and then describes how a verification flow based on Mentor’s CHI VIP, emulation operating system, hardware debugger and software debugger can be used to verify caches and fabrics that use this AMBA 5 protocol.

Presenter: William Orme, Strategic Marketing Manager, Systems & Software Group, ARM
Products: Questa
  • Debugging Software in Emulation
    Toggle Abstract

    TECHNICAL SESSION Mentor Graphic’s Veloce emulation system combined with the Questa verification solution is able to run designs in RTL orders of magnitude faster than simulation alone. As a result, emulation is used to execute verification runs which would be otherwise impossible in logic simulation. Often these verification runs will include some software executing on the design – as software is taking an increasing role in the functionality of a System-on-Chip (SoC). Software simply executes too slowly to practically run anything but the smallest testcase in the context of logic simulation. For example, booting embedded Linux on a typical ARM design might take 20 or 30 minutes in emulation. With significant software being executed in the context of the verification run, there needs to be some way to debug it. This session will cover the various methods which Mentor Graphic provides for debugging software in the context of emulation. These methods will include JTAG, the traditional method for debugging software on an emulated design; Codelink, which maximizes performance and emulation utilization; and Warpcore, which links virtual prototypes with emulation to deliver 100s of MIPS of software throughput – reducing Linux boot times from 20 minutes to mere seconds.

Presenter: Jim Kenney, Marketing Director, Mentor Graphics
Products: Veloce
  • Formal Apps In-Depth: Connectivity and Register Verification
    Toggle Abstract

    TECHNICAL SESSION Formal apps improve design quality and shorten the schedule for dealing with specific bottlenecks that occur during the verification process. In this session, we will discuss two of the most widely used apps in detail: connectivity verification and control and status register (CSR) verification. Come find out all you ever wanted to know about these apps, from someone who’s “been there, done that”!

Presenter: Mark Eslinger, Mentor Graphics
Products: Questa
  • Formal Verification Signoff Methodology
    Toggle Abstract

    TECHNICAL SESSION Formal sign-off is a relatively new concept in the industry. Like simulation sign-off, it requires a thorough and systematic methodology. This includes: end-to-end checkers, constraints, abstraction models and coverage points. This talk discusses each component of the formal sign-off methodology so that formal can be applied in the verification sign-off flow to maximize efficiency & productivity.

Presenter: Vigyan Singhal, President and CEO, Oski
Products: Questa
  • How off-the-shelf IP can cut time spent on PCIe verification in half
    Toggle Abstract

    TECHNICAL SESSION The presentation will highlight how PLDA, built a PCIe UVM/SystemVerilog-based verification environment and how the work reduced time spent on verification by a factor of two compared to PLDA’s previous Verilog/SystemVerilog-based environment.

Presenter: Romain Tourneau, PLDA
Products: Questa
  • Instant Formal Expert
    Toggle Abstract

    TECHNICAL SESSION What are formal property checking engines and how do they work? Why are they incredibly powerful for some properties, but not so good for others? What's the state of the art and what’s coming in the near future? In this talk, we'll review the fundamentals as well as the recent breakthroughs that are driving advances in performance and capacity. Join us to instantly become a formal expert!

Presenter: Jeremy Levitt, Engineering Manager, Mentor Graphics
Products: Questa
  • Maximize Verification Reuse with Portable Stimulus
    Toggle Abstract

    TECHNICAL SESSION Verification productivity and reuse are of key concern when verifying today’s complex designs. The ability to rapidly create large amounts of comprehensive test sequences at block, subsystem, SoC and system level are key to ensuring design quality. One key obstacle to achieving comprehensive testing today is the lack of a consistent stimulus specification that is reusable from block to system level. Recently, in response to industry demand, the Accellera Systems Initiative board launched a proposed working group to investigate whether to standardize a portable stimulus specification. This session will show how a portable stimulus specification brings 10-100x faster coverage closure to block level verification, and reusable comprehensive tests to SoC and system level verification

Presenter: Matthew Balance, Verification Technologist, Mentor Graphics
Products: Questa
  • Power exploration to RTL power convergence for advanced designs
    Toggle Abstract

    TECHNICAL SESSION Because over 80% of the final SoC/IP power is decided at the RT level, designers need to explore multiple power intent options and converge on power goals prior to place and route.  This presentation will discuss how Questa-Power Aware and Calypto PowerPro enables users to accurately analyze various power intent choices and then optimize for best power reduction at RTL without losing any functionality.

Presenter: Anand Iyer, Product Marketing, Calypto
Products: Questa
  • UVM Transactions - Important Undocumented Details
    Toggle Abstract

    TECHNICAL SESSION Fundamental questions most novice UVM users ponder include: Why uses classes instead of structs to define transactions for verification environments? What are advantages of using classes to represent transactions in a verification environment? Do I have to define different input and output classes for UVM testbenches? Why do I have to use do_methods() or field macros to override standard transaction methods? Why don't I just override the transaction methods directly? How do do_methods() and field macros work? SystemVerilog Guru and UVM expert, Cliff Cummings, will answer these questions and more to clarify many important details about UVM transactions.

Presenter: Cliff Cummings, President, Sunburst Design
Products: Questa
  • UVM: What’s New, What’s Next, and Why You Care
    Toggle Abstract

    TECHNICAL SESSION You may have heard there’s a new version of UVM that’s recently been released. This session will teach you everything you need to know about the future of UVM. We’ll briefly cover the new features included in UVM1.2 and how to minimize their impact, and we’ll identify the key subset of UVM features that will make your environment truly reusable from block to system-level verification while providing the ideal platform for integrating new solutions and standards.

Presenter: Tom Fitzpatrick, Verification Technologist, Mentor Graphics
Products: Questa
  • Verification and Debug: Old School Meets New School
    Toggle Abstract

    TECHNICAL SESSION “Old school” debug typically involves applying vectors directly to the design, a level of self-checking and then exploring the design with source, waves, and others to figure out what went wrong. With “new school” verification methodologies (UVM, randomization, golden reference models) the debug techniques need to be expanded. This session covers how you use the best of both worlds to find problems faster and to better answer “if you are done yet”.

Presenter: Rich Edelman, Verification Architect, Mentor Graphics
Products: Questa
  • You Think You Have Good Stimulus: System-Level Distributed Metrics Analysis and Results
    Toggle Abstract

    TECHNICAL SESSION Developing and maintaining an effective and efficient verification suite for a complex system requires the ability to measure, understand, and improve the environment. Distributed, hierarchical caches are an example of interacting components within an SoC. Understanding how well the components are verified is a challenge since the cache interactions are complex, the components are distributed across an environment, and the data is spread across one or more regressions. This session discusses the challenges of collecting metrics, providing the visualization to understand complex state machine interactions, and then reviews results of a regression analysis.

Presenter: Alan Hunter, ARM
Products: Questa