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Mentor@DAC 2013: AMS & Custom IC Design

Mentor Graphics provides advanced solutions for today’s most challenging Custom IC design and verification projects. Attend our AMS/Custom IC Design sessions to hear how other design teams are cutting months off their tape out schedules.

Mentor@DAC

Featured AMS/Custom IC Design Events

Tackling FinFET Analog Mixed Signal and Memory Verification Wednesday, June 4, 4:00 PM

Panel Analog, mixed-signal, and SRAM design teams migrating to FinFET process nodes are implementing new architectures to take advantage of FinFET benefits and overcome its limitations. As a result they need to retool their transistor-level verification flow for more accuracy, performance and capacity to offset the increased layout, device modeling, device noise, voltage scaling, and process variation effects. Designers of complex analog/mixed-signal circuits such as PLLs, ADCs, SerDes, and transceivers, need to explore alternative architectures and measure their impact in non-planar silicon. Embedded SRAM design teams realize that it is no longer acceptable to tolerate 5% or more inaccuracy in memory IP characterization. This panel is an interactive forum where attendees can exchange ideas and questions with a group of experts who are tackling the exciting opportunities and challenges related to the move to FinFET nodes.

F = Full registration required

Experts @ the Booth
  • Custom IC Design and AMS Simulation/Verification – Unparalleled Insight and Productivity
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    TECHNICAL SESSION From our complete Custom IC Design flow through our industry leading simulators and analog/ mixed-signal verification systems, Mentor solutions provide insight and productivity.  This session provides an overview of the analog/mixed-signal product portfolio with an emphasis on new capabilities, recent customer results, and a future vision.  We introduce the newest member of the portfolio, the Analog FastSPICE Platform from Berkeley Design Automation (BDA), now part of Mentor.

Presenter: Tom Daspit, Mentor Graphics
Products: Pyxis, Analog FastSPICE (AFS) Platform, Eldo, ADit
  • Introduction to the Analog FastSPICE (AFS) Platform
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    TECHNICAL SESSION The latest addition to the Mentor analog/mixed-signal simulation and verification family is the Analog FastSPICE (AFS) Platform developed by Berkeley Design Automation (BDA), now part of Mentor. This session provides details on the AFS Platform, the world’s fastest circuit verification for nanometer analog, RF, mixed-signal, and custom digital circuits. Foundry certified to 16nm/14nm FinFET-based processes, the AFS Platform delivers nanometer SPICE accuracy 5x-10x faster than traditional SPICE and 2x-6x faster than parallel SPICE simulators. For large analog/mixed-signal circuits, the AFS Platform delivers greater than 10M-element capacity and the fastest mixed-signal simulation. For silicon-accurate characterization, it includes the industry’s only full-spectrum, device noise analysis and delivers near-linear performance scaling with the number of cores. Come hear what Analog FastSPICE can do for your analog/mixed-signal design and verification flow.

Presenter: Mick Tegethoff, Mentor Graphics
Products: Analog FastSPICE (AFS) Platform
  • PyxisOpen — Assisted Automation for the Toughest Custom IC Design Problems
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    TECHNICAL SESSION Mentor is bringing revolutionary insight and automation to the most intensively manual portion of custom IC design with PyxisOpen’s new OpenAccess (OA) based automation core. Learn how our interactive custom router boosts productivity as it shortens routing time by 10X and cuts weeks off tapeout schedules. See a demo of our OA-based automation core and Calibre RealTime integration. 

Presenter: Tom Daspit, Mentor Graphics
Products: PyxisOpen
  • Tackling FinFET Analog Mixed Signal and Memory Verification
    Toggle Abstract

    PANEL Analog, mixed-signal, and SRAM design teams migrating to FinFET process nodes are implementing new architectures to take advantage of FinFET benefits and overcome its limitations. As a result they need to retool their transistor-level verification flow for more accuracy, performance and capacity to offset the increased layout, device modeling, device noise, voltage scaling, and process variation effects. Designers of complex analog/mixed-signal circuits such as PLLs, ADCs, SerDes, and transceivers, need to explore alternative architectures and measure their impact in non-planar silicon. Embedded SRAM design teams realize that it is no longer acceptable to tolerate 5% or more inaccuracy in memory IP characterization. This panel is an interactive forum where attendees can exchange ideas and questions with a group of experts who are tackling the exciting opportunities and challenges related to the move to FinFET nodes.

Products: Analog Mixed Signal