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Design & Functional Verification

Technology and economics are driving the move up in abstraction from chip design to system design and from RTL to HLS. Design creation and verification automation capabilities are being adapted to the new level of design abstraction. Simultaneously, smarter verification automation improves productivity. Attend our Design/Functional Verification and Verification Academy sessions to discover new automation opportunities.

Featured Design & Functional Verification Events

Get Your FPGA Out of the Lab and into Production Monday, June 2, 9:00 AM

Technical Session Spending too much time in the Lab debugging your FPGA? FPGA’s have grown large and complex. So, too has the task of validating the functionality after it has passed all the tests for area, performance, and power. If there is a problem with your FPGA, where do you start looking? Combined with the powerful capabilities of the Mentor FPGA design flow spanning from design capture, implementation, and board design, come join us as we introduce new methods to not only produce better quality FPGA designs but also new methods and tools to help you instrument your FPGA design so that problems are easier to find as they happen.

Full SoC Emulation from Device Drivers to Peripheral Interfaces Monday, June 2, 10:00 AM

Technical Session Companies have added a tape out requirement that ensures their SoC executes the OS loader to a boot prompt. Thus, verification of HW/SW interactions is no longer just a good idea, it’s a hard requirement. The methods for executing and debugging OS boot and device driver software on hardware during emulation are evolving rapidly. This session contrasts live versus off-line SW debug tools in the context of multi-core SoC designs, and physical versus virtual peripheral models as device driver targets. Participants will come away with an understanding of how an emulation-based, end-to-end flow yields a higher confidence at tape out and a faster time to market.

100% Verified But the Chip Failed – Why? Monday, June 2, 4:00 PM

Technical Session You reached 100% coverage on your chip so why did it still fail? The problem may lie within your design process. Design flaws found late in the design cycle or, even worse, in the field or production, are not only costly, but could pose safety risks.  Mentor’s solution starts at the beginning – with the design requirements. Not verifying to the requirements can result in untested or incorrectly implemented aspects of the design. This session walks you through a repeatable requirements validation approach to verify 100% to the requirements.

F = Full registration required

Experts @ the Booth
  • 100% Verified But the Chip Failed – Why?
    Toggle Abstract

    TECHNICAL SESSION You reached 100% coverage on your chip so why did it still fail? The problem may lie within your design process. Design flaws found late in the design cycle or, even worse, in the field or production, are not only costly, but could pose safety risks.  Mentor’s solution starts at the beginning – with the design requirements. Not verifying to the requirements can result in untested or incorrectly implemented aspects of the design. This session walks you through a repeatable requirements validation approach to verify 100% to the requirements.

Presenter: Valerie Rachko, Marketing Director, Mentor Graphics
Products: ReqTracer, HDL Designer
  • Block-to-System Verification of ARM-Based SoCs
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    TECHNICAL SESSION SoCs incorporate ARM processor and fabric IP to meet requirements in functionality and time-to-market. Employing excellent functional verification solutions from block design to system verification ensure SoCs deliver required functionality and within schedule. Mentor Graphics will discuss functional verification solutions spanning from block-level verification to full system verification.

Presenter: Steve Bailey, Director of Emerging Technologies, Mentor Graphics
Products: Questa
  • Full SoC Emulation from Device Drivers to Peripheral Interfaces
    Toggle Abstract

    TECHNICAL SESSION Companies have added a tape out requirement that ensures their SoC executes the OS loader to a boot prompt. Thus, verification of HW/SW interactions is no longer just a good idea, it’s a hard requirement. The methods for executing and debugging OS boot and device driver software on hardware during emulation are evolving rapidly. This session contrasts live versus off-line SW debug tools in the context of multi-core SoC designs, and physical versus virtual peripheral models as device driver targets. Participants will come away with an understanding of how an emulation-based, end-to-end flow yields a higher confidence at tape out and a faster time to market.

Presenter: Jim Kenney, Marketing Director, Mentor Graphics
Products: Veloce
  • Get Your FPGA Out of the Lab and into Production
    Toggle Abstract

    TECHNICAL SESSION Spending too much time in the Lab debugging your FPGA? FPGA’s have grown large and complex. So, too has the task of validating the functionality after it has passed all the tests for area, performance, and power. If there is a problem with your FPGA, where do you start looking? Combined with the powerful capabilities of the Mentor FPGA design flow spanning from design capture, implementation, and board design, come join us as we introduce new methods to not only produce better quality FPGA designs but also new methods and tools to help you instrument your FPGA design so that problems are easier to find as they happen.

Presenter: Jim Kenney, Marketing Director, Mentor Graphics
Products: HDL Designer, Precision, Questa
  • How to Accelerate Verification with 5 Easy to Use Formal Apps
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    TECHNICAL SESSION What if you could harness the benefits of formal verification without the pain? That’s exactly what Questa’s fully-automatic formal apps allow you to do. This session presents the top 5 apps used to get better quality designs out the door faster. We’ll review apps for: (1) Clock-domain crossings, (2) Common RTL coding errors, (3) X-states, (4) Coverage closure, (5) Property generation.

Presenter: Roger Sabbagh, Product Marketing Manager, Mentor Graphics
Products: Questa
  • Innovative Virtual Prototype Technologies for System and Application Bring-up
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    TECHNICAL SESSION Traditional embedded system design is transforming to a new world of Virtual embedded software and hardware design. Mentor’s virtual prototyping solution is revolutionizing embedded platform-based design by enabling debug of hardware/software complex interactions and by providing analysis capabilities not achievable with traditional simulation or on prototyping boards. It offers a tightly coupled HW/SW debug, analysis and verification capabilities that are changing the traditional design paradigm on prototyping boards. This includes observing the behaviour of the platform’s software in a non-intrusive manner, without introducing any observation effects. This session will illustrate the level of control, visibility and analysis capabilities available on a reference virtual prototype to guide efficient software and hardware development that meets the functionality and performance goals.

Presenter: Shabtay Matalon, Market Development Manager, Mentor Graphics
Products: Vista, CodeBench-Virtual Edition
  • Mentor Graphics Formal Verification Meets the Need for Complex Designs
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    TECHNICAL SESSION The latest research on formal verification has resulted in new and more powerful algorithms to solve the challenges of verifying very complex designs that are not well addressed by traditional methods. Tools like Mentor’s Questa Formal have also evolved to make it easy to apply formal verification to specific use cases. In this session we’ll show Samsung case studies that demonstrate how formal verification tools improve project schedules and design quality.

Presenter: Roger Sabbagh, Product Marketing Manager, Mentor Graphics
Products: Questa
  • Questa: High-Performance Simulation, Emulation and much more
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    TECHNICAL SESSION With the growing size, complexity and software content of today’s SoC designs, verification requires a platform that gives you more than just simulation. Come see how Questa ties simulation, formal and emulation together and brings testbench automation, coverage closure, low power, abstract portable stimulus, new system-level metrics and more to maximizes your verification productivity.

Presenter: Mark Olen, Product Marketing Manager, Mentor Graphics
Products: Veloce, Questa
  • Vista Virtual Prototyping for HW/SW Debug and Analysis
    Toggle Abstract

    TECHNICAL SESSION Traditional embedded system design is transforming to a new world of Virtual embedded software and hardware design. Mentor’s virtual prototyping solution is revolutionizing embedded platform-based design by enabling debug of hardware/software complex interactions and by providing analysis capabilities not achievable with traditional simulation or on prototyping boards. It offers a tightly coupled HW/SW debug, analysis and verification capabilities that are changing the traditional design paradigm on prototyping boards. This includes observing the behaviour of the platform’s software in a non-intrusive manner, without introducing any observation effects.
    This session will illustrate the level of control, visibility and analysis capabilities available on a reference virtual prototype to guide efficient software and hardware development that meets the functionality and performance goals.

Presenter: Shabtay Matalon, Market Development Manager, Mentor Graphics
Products: Vista, CodeBench-Virtual Edition
  • Visualizer: A Powerful Debug Environment for Complex SOCs
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    TECHNICAL SESSION This session will focus on improving debug productivity with Visualizer, Mentor’s NEW high performance and capacity debug environment. Visualizer is tightly integrated with both Questa simulation and Veloce emulation to improve debug productivity for RTL, gates and SV/UVM testbenches. Visualizer is fast and intuitive with powerful, automated features that help pinpoint the cause of errors and explore your design.

Presenter: Anissa Mawer, Verification Technology Manager, Mentor Graphics
Products: Veloce, Questa, Visualizer
Experts @ the Conference
  • End-User Applications - Tests for Nothing and Verification for Free F
    Toggle Abstract

    PANEL To verify an IP one can create new tests  or extract IP-level tests from existing application software. So far, verification teams have been creating new tests for each new IP. While highly efficient tests can be created , the process is time consuming. The alternative of test extraction is inefficient. But, what if the process of extracting IP-level tests from application software were automated?  A large trove of tests would be readily available even before a new IP development began. One camp believes that extraction  is an old idea: it never has worked because it is not efficient. Another camp believes that today this is possibly the only way to complete verification on time. Who holds the winning approach?

Presenter: Harry Foster, Chief Verification Scientist, Mentor Graphics
Products: Questa
  • Power Aware Clock Domain Crossing Verification F
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    TECHNICAL SESSION Formal and static methods, which analyze a design directly rather than depending on large numbers of simulation vectors, are becoming increasingly important in the world of modern design. In the first part of this session, real-world practitioners who have been successful with formal verification describe case studies and use them to supply useful advice for those who wish to achieve similar results. Then we move on to describe some new and powerful uses for static and formal techniques in conjunction with other tools and methods, providing new insights into IP integration, clock domain crossings, power issues, and clock/reset design.

Presenter: Roger Sabbagh, Product Marketing Manager, Mentor Graphics
Presenter: Saumitra Goel, Lead Consultant Staff, Mentor Graphics
Products: Questa