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Mentor@DAC 2013: IC Design & Test

IC Design and Test—Opportunities and Challenges in the Coming Year

These are exciting times for IC and systems designers! At 20nm we will have billions of transistors on a single die at our disposal, and emerging 3D-IC techniques will enable us to stack chips to create small, affordable systems of incredible power and flexibility that will drive electronics industry growth. However, there will be some big challenges along the way.

At this year’s DAC, Mentor will share EDA techniques and technologies, developed in partnership with the world’s largest design houses and foundries, that will help make you successful at the leading edge of IC development.

Mentor@DAC

Featured IC Design & Test Events

Back to the Future: Is There Success without Moore's Law? Monday, June 2, 4:00 PM

Panel There seems to be a lot of angst in the industry over the increasing costs of extending IC scalability. For decades, the success of our industry has been predicated on Moore’s Law—the ability to deliver exponentially increasing logic density at continuously decreasing costs. Can the industry be successful without this virtuous cycle? The reality is that many players are doing very well without pushing the leading edge of scalability. This panel will look at the ways that IC innovators are adding value to established IC nodes through increasing functionality, reduced power consumption, higher reliability, integration of MEMS and silicon photonics, and die stacking. Come and pick up some new ideas from our panel while you’re enjoying Happy Hour at the Mentor booth.

What will Moore's Law Cost Us at 10nm? Tuesday, June 3, 4:00 PM

Panel For the first time in many years, there is a lot of uncertainty about how we get to the next IC scaling nodes. Will EUV be ready? Will we have to go to triple or quadruple patterning? Can DSA be commercialized quickly enough? What are the cost implications for these various alternatives? Can we see a way to get to 10nm and 7nm with an affordable technology? Are we at the point where designs are so tightly linked to a manufacturer’s specific process that multi-sourcing is unfeasible? How much commonality is there, and what can tools do to hide the differences? If it’s doable, is multi-sourcing economically viable? This panel will consider these all important questions and provide some insights if not the final answers. Be prepared for a wide open discussion and some big differences of opinion. Come and get engaged in the discussion while you’re enjoying Happy Hour at the Mentor booth.

F = Full registration required

Experts @ the Booth
  • Back to the Future: Is There Success without Moore's Law?
    Toggle Abstract

    PANEL There seems to be a lot of angst in the industry over the increasing costs of extending IC scalability. For decades, the success of our industry has been predicated on Moore’s Law—the ability to deliver exponentially increasing logic density at continuously decreasing costs. Can the industry be successful without this virtuous cycle? The reality is that many players are doing very well without pushing the leading edge of scalability. This panel will look at the ways that IC innovators are adding value to established IC nodes through increasing functionality, reduced power consumption, higher reliability, integration of MEMS and silicon photonics, and die stacking. Come and pick up some new ideas from our panel while you’re enjoying Happy Hour at the Mentor booth.

Presenter: Michael Buehler-Garcia, Senior Director of Marketing for Calibre Design Solutions, Mentor Graphics
Products: Calibre
  • Better Layout in Less Time: AMD’s Experience with Calibre RealTime at 20nm and Below
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    TECHNICAL SESSION Physical implementation is significantly more challenging at 20nm than at previous nodes. Introducing Calibre RealTime into the production flow at AMD enabled designers to meet this challenge and improve the quality of the layout at the same time. Calibre RealTime provides immediate feedback for implementation and the ability to optimize the layout with full sign-off feedback. This enables us to make last-minute edits with sign-off confidence, and to reduce the number of batch DRC iterations required to reach tape-out.

Presenter: Kalyan Chakravarthy, Member of Technical Staff, AMD
Presenter: Srinivas Velivala, Calibre TME, Mentor Graphics
Products: Calibre RealTime
  • Calibre Advanced Physical Verification: Learn What’s Coming Your Way at 16/14nm and 10nm and How Calibre is Already Prepared
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    TECHNICAL SESSION Physical verification (PV) complexity continues to grow by leaps and bounds as customers move to the advanced nodes that require multi-patterning and more recently FinFETs. Come learn about the emerging trends in PV and how the Calibre nmPlatform continues to rapidly expand, addressing the needs for advanced PV and helping you get your design to market faster.

Presenter: Michael White, Director of Product Marketing, Calibre Physical Verification Products, Mentor Graphics
Products: Calibre nmDRC
  • Improving Circuit Reliability with Calibre PERC
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    TECHNICAL SESSION Circuit reliability continues to be a focus for all process nodes. Verification techniques that extend beyond traditional DRC, LVS and ERC checks are needed to meet the demands of today’s designs. Device and interconnect reliability solutions that are scalable across many designs without the need for manual intervention improves the repeatability and efficiency of these checks. Come see how we leverage unique technology with foundry-provided rule decks to solve some of the most challenging reliability concerns IC designers face. We will also discuss electrical overstress (EOS), current density and electromigration issues, to name a few, which can be solved by the comprehensive Calibre PERC reliability verification platform.

Presenter: Matt Hogan, Product Marketing Manager, Calibre Design Solutions, Mentor Graphics
Products: Calibre PERC
  • Mentor RTL to GDS Digital Implementation for Best PPA at Advanced Nodes
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    TECHNICAL SESSION Achieving best power, performance and area (PPA) has gotten significantly more difficult at advanced nodes (20/16nm and below) due to inherent challenges . At smaller nodes the traditional design closure flow is inadequate due to complex DRC and DFM rules, multi-patterning (MP) and FinFET requirements, growing design sizes, low power requirements, high performance targets and increasing process and design variations. This session will highlight some of the advanced Oasys RealTime Designer(tm) and Olympus-SoC(tm) technologies to achieve best PPA and efficient RTL-to-GDS design closure. We will focus on unique technologies such as MP and FinFET aware implementation, high capacity RTL synthesis, RTL floorplanning, concurrent PPA optimization for best QoR, and DRC/DP signoff during implementation.

Presenter: Arvind Narayanan, Product Marketing Manager, Integrated Circuit Implementation Division, Mentor Graphics
Presenter: Shankar Vellanthurai, Mentor Graphics
Products: IC Design & Test
  • Not Jumping to 16/14nm Tomorrow? Extend the Lifetime and Get the Most Out of Established Nodes with Advanced Calibre
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    TECHNICAL SESSION With the costs and complexity of 20nm and below, customers are staying longer at established nodes (e.g. 90nm – 28nm). They are also pushing much more complex designs through these nodes than ever before. Come learn how Calibre has solutions to help you get the most out of established processes for your next design.

Presenter: John Ferguson, Director of Marketing, Calibre DRC Applications, Mentor Graphics
Products: Calibre nmDRC
  • Parasitic Extraction to Meet the Challenge of Advanced Nodes
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    TECHNICAL SESSION The world is 3D! Leading edge designers are considering new designs at advanced process nodes with 3D transistors (FinFETs). Others are considering “More than Moore” and opting for a 3D-IC approach. Everyone wants more accuracy which implies 3D modeling techniques to achieve high correlation against reference results. With these new challenges come traditional concerns of turn-around time (TAT), growing design complexity, double-patterning and growing number of interconnect corners that add to the challenge of robust parasitic extraction. This session will describe how new methods in Calibre have been developed to address these challenges and meet the performance, accuracy, and usability concerns for designers at all nodes.

Presenter: Carey Robertson, Director of Product Marketing, LVS and Extraction, Mentor Graphics
Products: Calibre nmLVS, Calibre xACT
  • Samsung Ecosystem Collaboration with Mentor for DFM at 14nm and Below
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    TECHNICAL SESSION For the 14nm node, Mentor and Samsung have collaborated extensively to create a comprehensive DFM solution that includes proven solutions for litho simulation, pattern matching, critical area analysis (CAA) and advanced filling. Come to this session to understand what was done and how it can help you move to 14nm.

Presenter: Jean-Marie Brunet, Product Marketing Director for Design for Manufacturing (DFM) and Place & Route Integration, Mentor Graphics
Presenter: Kuang-Kuo Lin, Director of Foundry Design Enablement at America Headquarters Device Solutions, Samsung Semiconductor
Products: Calibre LFD, Calibre YieldEnhancer, Calibre YieldAnalyzer
  • Tessent Support of ARM Cores and Memories_x000D_
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    TECHNICAL SESSION Mentor Graphics and ARM are partnering to provide customers with tools to deliver the most advanced, defect free and highest yielding IC products to market in a timely manner. The two companies continue to work to ensure Mentor’s Tessent family of silicon test products are optimized to provide comprehensive and cost-effective test coverage of ARM processors and memory IP. This presentation will describe test solutions developed to cover both the memory and logic test requirements of ARM-based designs. Special emphasis will be placed on the automated support of the ARM standardized MBIST (aka Shared Bus) core interface. This interface enables test access to memories through the functional path, resulting in higher quality test and reduced impact on performance.

Presenter: Steve Pateras, Product Marketing Director, Silicon Test Products, Mentor Graphics
Products: Tessent
  • Test Solutions for High-Quality Automotive Devices
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    TECHNICAL SESSION The growing amount of electronics within today’s automobiles is driving very high quality and reliability requirements to a widening range of semiconductor devices. Improvements in test solutions are needed not only to maintain very high quality levels in more advanced technology nodes but to also address increasing reliability requirements such as defined within the ISO 26262 standard. New test approaches to be described will include a new hybrid ATPG compression and logic BIST solution that provides more efficient defect coverage together with the ability to apply tests within the system for long-term reliability. This hybrid solution also supports a new cell-aware test generation approach that has been shown to significantly reduce DPM levels in shipped devices.

Presenter: Steve Pateras, Product Marketing Director, Silicon Test Products, Mentor Graphics
Products: Tessent
  • The Challenges of Power Grid Design in Advanced ICs
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    TECHNICAL SESSION Power analysis has assumed a much more important and demanding role in the IC design flow. Exploding design sizes and complexity combined with a host of new analysis requirements has made this a very challenging design task. Designers need to analyze the impact of IR drop and current in-rush on signal integrity, current density and electro-migration impact on reliability, and other power-related issues. This session will review current issues with power analysis and discuss the capabilities needed to address them.

Presenter: Christen Decoin, Product Marketing Manager for New and Emerging Markets, Mentor Graphics
Products: Calibre
  • Update on DFM and Fill for Advanced Nodes
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    TECHNICAL SESSION At 28 nm and below, litho process checking (LPC), CMP analysis and critical area analysis (CAA) are all crucial steps to help ensure manufacturability. In addition, layout fill has become a more complex and critical issue. Come to this session to understand today’s DFM issues, to find out what is required by the foundries at each node, to learn about updates to DFM tools, and to see how SmartFill is changing the approach to fill at advanced nodes.

Presenter: Jeff Wilson, DFM Product Marketing Manager, Mentor Graphics
Presenter: Joe Kwan, Foundries Program Manager, Mentor Graphics
Products: Calibre LFD, Calibre YieldEnhancer, Calibre YieldAnalyzer
  • What will Moore's Law Cost Us at 10nm?
    Toggle Abstract

    PANEL For the first time in many years, there is a lot of uncertainty about how we get to the next IC scaling nodes. Will EUV be ready? Will we have to go to triple or quadruple patterning? Can DSA be commercialized quickly enough? What are the cost implications for these various alternatives? Can we see a way to get to 10nm and 7nm with an affordable technology? Are we at the point where designs are so tightly linked to a manufacturer’s specific process that multi-sourcing is unfeasible? How much commonality is there, and what can tools do to hide the differences? If it’s doable, is multi-sourcing economically viable? This panel will consider these all important questions and provide some insights if not the final answers. Be prepared for a wide open discussion and some big differences of opinion. Come and get engaged in the discussion while you’re enjoying Happy Hour at the Mentor booth.

Presenter: Joe Sawicki, Vice President and General Manager Design to Silicon Division, Mentor Graphics
Products: Calibre
Experts @ the Conference
  • Advanced Layout Reliability Verification Methodology For Mixed Signal and Multi-Power Domain Designs F
Presenter: HungHsu Feng, Mentor Graphics
Presenter: Jen Chen, Mentor Graphics
Presenter: Srinivas Velivala, Calibre TME, Mentor Graphics
Products: Calibre
  • Challenges in Applying Machine Learning Techniques and Data Mining in Physical Verification F
    Toggle Abstract

    TECHNICAL SESSION Data mining is the process of extracting previously-unknown interesting patterns from large quantities of data. Data mining is particularly applicable to problems that involve discovering trends, anomalies and/or dependencies in the data. Many such problems occur in the context of EDA, e.g., in functional verification, timing analysis, physical verification, test, debug and diagnosis. This session begins with an overview of data mining techniques, the types of problems they solve and their potential applications in EDA. The introduction is followed by two talks that provide in-depth discussion in specific areas. The first focuses on test and functional verification. It overviews promising applications and shares experiences implementing a data-mining-based methodology in several industrial applications. The second focuses on physical verification and addresses practical applicability and limitations of data-mining using hot-spot detection as an example.

Presenter: Andres Torres, Mentor Graphics
Products: Calibre
  • Designing In Security: What Will It Take? F
    Toggle Abstract

    PANEL The security and trustworthiness of everything from large-scale servers in the cloud to the lock on a hotel room are of growing concern. With the proliferation of intelligent, networked devices and systems, the “hardware root of trust” is a vital component of overall security. A panel of industry experts will provide perspectives on the challenges to development and adoption of strategies and techniques for Designing In Security, and research that is needed to accelerate progress. A new industry consortium on Trustworthy and Secure Semiconductors and Systems (T3S) that is partnering with government to support fundamental research also will be discussed.

Presenter: Joachim Langenwalter, Mentor Graphics
Products: Calibre
  • Fast and Accurate Full-chip Extraction and Optimization of TSV-to-Wire Coupling F
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    TECHNICAL PAPER This session covers topics from transistor-level to circuit-level modeling in 2D and 3D IC designs.

Presenter: Dusan Petranovic, Mentor Graphics
Presenter: Sung Kyu Lim, Georgia Institute of Technology
Presenter: Yarui Peng, Georgia Institute of Technology
Products: Calibre
  • FinFET and IC Design: Mountain or Mole Hill? F
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    PANEL FinFETs have moved from the industry roadmap into industry deployment. The test chips are back. Many designs are underway. The 14nm process is being projected to tighter rules that will bring even more concerns about FIN gate performance, depending on many factors such as sidewall and FIN characteristics, including pitches and height to mention some. The pressing questions from many are: how big of a deal are FinFETs to my design process? How is the EDA industry responding to design needs to predict the impact of the FIN parameters in device performance, reliability and manufacturability in general?

Presenter: Jean-Marie Brunet, Product Marketing Director for Design for Manufacturing (DFM) and Place & Route Integration, Mentor Graphics
Products: Calibre
  • Geometric Pattern Match Using Edge Driven Dissected Rectangles and Vector Space F
Presenter: Robert Todd, Mentor Graphics
Products: Calibre
  • Modeling Proximity-Induced Variability in Standard Cells for Optimized Timing Performance F
Presenter: Mohamed Dessouky, Mentor Graphics
Presenter: Mohamed Said, Mentor Graphics
Products: Calibre
  • On Timing Closure: Buffer Insertion for Hold-Violation Removal F
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    TECHNICAL PAPER This session discusses some key challenges in timing closure and future generation physical design. The first two papers specifically discuss physical challenges of 3D ICs in terms of design methodologies, performance and packaging while the remaining papers present new techniques and algorithms for timing closure of high-performance designs.

Presenter: Ivailo Nedelchev, Mentor Graphics
Presenter: Sarvesh Bhardwaj, Mentor Graphics
Presenter: Vidyamani Parkhe, Mentor Graphics
Products: Calibre
  • On Using Implied Values in EDT-Based Test Compression F
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    TECHNICAL PAPER If process variations, defects or test costs keep you up at night, this is your chance to face your demons. This session introduces novel test methods to uncover defects, diagnosis strategies to pinpoint failure root-cause and calibration techniques to compensate for manufacturing imperfections.

Presenter: Grzegorz Mrugalski, Mentor Graphics
Presenter: Janusz Rajski, Mentor Graphics
Presenter: Jerzy Tyszer, Poznan University of Technology
Presenter: Marcin Gebala, Poznan University of Technology
Presenter: Nilanjan Mukherjee, Mentor Graphics
Products: Calibre
  • Physical Verification of Hierarchical Analog Design Constraints for Automotive ICs F
Presenter: Dina Medhat, Mentor Graphics
Presenter: Hartmut Marquardt, Mentor Graphics
Products: Calibre
  • Stress Assessment for Device Performance in 3D IC F
Presenter: Armen Kteyan, Mentor Graphics
Presenter: Gevorg Gevorgyan, Mentor Graphics
Presenter: Henrik Hovsepyan, Mentor Graphics
Presenter: Jun-Ho Choy, Mentor Graphics
Presenter: Valeriy Sukharev, Mentor Graphics
Products: Calibre