Mentor@DAC 2013: IC Design & Test

PARTNER KIOSK PRESENTATION One of the predominant P&R challenges is realizing best power, performance and area (PPA), a goal that is more difficult to achieve at advanced nodes due to complex DRC / DFM rules, double patterning, growing design sizes, low power requirements and increasing process and design variations. It is also critical to reduce the die size to justify the cost of moving to smaller nodes. This session shows advanced technologies for efficient design closure such as concurrent PPA optimization, pseudo flat flow methodology and DRC/DP signoff during implementation.

SUITE SESSION The parasitic extraction flow is being challenged on a number of fronts: the need for higher accuracy at smaller dimensions, the complexity of high transistor and gate counts and more extensive fill, the impact of double patterning on modeling and accuracy, the need for new models for FinFETs and Through Silicon Via (TSVs), and the need to handle ECOs in an fast and efficient manner. This session will describe these new challenges and also new approaches to PEX that can deliver the required capabilities while significantly reducing turnaround time.

SUITE SESSION TowerJazz, the global specialty foundry leader, is now providing Calibre PERC rule decks that enable their customers to perform circuit reliability verification during signoff. TowerJazz provides highly customized electrostatic discharge (ESD) and power management circuit checks based on their specific manufacturing processes. Many of these checks have been automated for the first time by taking advantage of the Calibre PERC product’s unique ability to combine schematic (net list) and physical layout information, which goes beyond the scope of traditional LVS, DRC and ERC tools. This is a one-time, limited seating session for advanced Calibre users. Register today to reserve your spot.

SUITE SESSION When leading edge customers first transitioned to 20nm they encountered issues not experienced in prior nodes with the set-up of hardware, flows, and use models during chip verification. TSMC and Mentor worked with these customers to resolve the issues resulting in successful tape-outs of these customers’ designs. TSMC and Mentor will present best practices learned from that experience to help other customers smoothly tape-out their advanced process node designs.

SUITE SESSION Implementing a robust IC verification methodology that addresses circuit reliability is increasingly difficulty for all process nodes. Larger nodes are seeing new challenges that were not apparent in previous generations, such as increasing design complexity. Smaller nodes are seeing greater sensitivity to electrical overstress (EOS), current density and electro-migration issues. For designs with multiple complex power domains, transistor-level power intent verification can be difficult to verify, but new tools are emerging to automate such checking by leveraging UPF. This session describes how Calibre PERC can provide a comprehensive reliability verification platform to address these problems.

SUITE SESSION At 28 nm and below, litho process checking (LPC), CMP analysis and critical area analysis (CAA) are all crucial steps to help ensure manufacturability. In addition, layout fill has become a more complex and critical issue. While in the past the goal was simply to insert minimum fill to maintain planarity, today you need to maximize fill and place and orient it precisely to optimize its benefits. Come to this session to understand today’s DFM issues, to find out what is required by the foundries at each node, to learn about updates to DFM tools, and to see how SmartFill is changing the approach to fill at advanced nodes.

SUITE SESSION ISO 26262 is emerging as a standard that’s being rapidly adopted by the automotive industry. This standard specifies objectives that must be met in the development of safety critical automotive electronics systems. This standard is already starting to push new requirements down to the semiconductor suppliers for these automotive subsystems. This is creating an opportunity for automotive semiconductor suppliers to differentiate themselves based on their test strategy, which can make their offering more appealing for ISO 26262 mandated systems. This session will focus on features and solutions within Mentor Graphics’ Tessent silicon test and yield analysis products that can be leveraged for designs destined for an ISO 26262 application.

SUITE SESSION With the growing design sizes at advanced nodes, top level chip assembly and optimization is done  using abstracts without the full chip context. This is an highly iterative and manual process that can have a noticeable huge impact on design turn-around time and QoR. In this session we will discuss the chip assembly solution from Olympus-SoC P&R platfomr including key technologies such as top level concurrent MCMM optimization, Synchronous optimization for replicated partitions, top level clock tuning and layer promotion of critical nets for faster timing convergence and design closure.

PARTNER KIOSK PRESENTATION 3D transistors, or FinFETs, exacerbate concerns about quality and reliability at 16nm and below. While there has already been a lot of research into the types of defects expected with FinFETs, characterizing these defect mechanisms is only the first step. We also need a methodology for generating test patterns that efficiently target these new defects. This session will describe the use of the cell-aware test approach to meet this test requirement.

PARTNER KIOSK PRESENTATION The ability to effectively identify yield limiting design feature is a key asset for foundries and fabless semiconductor companies. This presentation covers the result of a collaboration between Mentor Graphics and GLOBALFOUNDRIES to rapidly identify systematic defects and critical design features based on silicon data [1-4]. Layout-aware diagnosis identifies the location and classification of defects causing manufacturing test failures. Specialized statistical analysis coupled with design profiling data (such as critical feature analysis) then determines the root cause of yield loss and separates design and process induced defects.

SUITE SESSION Designing a quantum photonic imagers poses a unique challenge to the P&R designers due to the inherent nature of the stacked die interface. This technology has a high density of signal interfaces driven by Analog macros that pose a big challenge during P&R from both a floorplanning and routing perspective. This session will talk about the full netlist to GDS implementation of the photonic imager design done using Olympus. The session will also cover how Olympus was able to handle the unique design requirements specifically from a floorplanning and routing standpoint, and was able to successfully achieve design closure.

SUITE SESSION One of the predominant place and route challenges is realizing best power, performance and area (PPA), a goal that has gotten significantly more difficult to achieve at advanced nodes (20nm and below). At smaller technology nodes the traditional design closure flow is inadequate due to complex DRC / DFM rules, double patterning requirements, growing design sizes, low power requirements and increasing process and design variations. In addition to solving these challenges, it is also critical to achieve high utilization and reduce the die size to justify the cost of moving to smaller nodes. This session will highlight some of the advanced Olympus-SoC technologies to achieve efficient design closure with unique technologies such as concurrent PPA optimization, pseudo flat flow methodology and DRC/DP signoff during implementation.

PARTNER KIOSK PRESENTATION Successful IC manufacturing at 20nm requires some important design optimization strategies. Fill becomes much more sophisticated because it’s no longer just about planarity, but a whole range of interrelated effects, such as etch, lithography, stress, and rapid thermal annealing (RTA). Verification of latch-up immunity depends on automated measurements and analysis, for example, determining the resistance of paths in output driver arrays as a function of device spacing. Other circuit checks address reliability issues, including electrostatic discharge (ESD), electrical overstress (EOS), and errors arising from signals crossing multiple power domains. This session will highlight areas where Mentor and GLOBALFOUNDRIES have collaborated to deliver solutions to new design enabling challenges.

SUITE PANEL Several high growth IC markets are experiencing demand for higher reliability, including mobile/wireless, automotive, industrial control and medical. At the same time, factors such as thinner gate oxide and multiple power rails have the potential to introduce subtle design flaws leading to delayed failure mechanisms. This panel will be an interactive forum where experts and attendees on the show floor can discuss the demand for IC reliability, what design methodologies can reduce the occurrence of delayed failure mechanisms, and how design for reliability checks can be automated to help remove the burden from designers. The panel will be immediately followed by a hosted bar happy hour.

SUITE PANEL The IC industry will undergo significant changes as future growth is driven not just by traditional Moore’s Law scaling, but also by “More Than Moore” technologies including 3D-IC, MEMS and silicon photonics. As these technologies emerge from R&D into volume production, they will create new opportunities for IC designers to add value to products. They will also challenge designers to find a way to combine the strengths of these technologies and to marry them into a unified EDA flow. This panel will be an interactive forum where attendees on the exhibition floor can exchange ideas and questions with a group of experts who are already grappling with these exciting opportunities and challenges. The panel will be immediately followed by a hosted bar happy hour.

SUITE PANEL FinFETs, or so-called 3D transistors, are a key competitive element in all the leading edge IC foundry offerings because FinFETs can achieve much lower power operation than planar transistors. There has been a lot of discussion of the physical and electrical characteristics of FinFETs, but designers are wondering how FinFETs will change the design, verification and test flow. This show floor panel will provide a forum for experts and DAC attendees to learn and interact directly in an informal and entertaining discussion. The panel will be immediately followed by a hosted bar happy hour.

SUITE SESSION In this session STMicroelectronics will be sharing their experience and successes in using Olympus-SoC on their designs. They will be specifically covering the key backend design challenges and how Olympus was effectively used for timing and design closure including MCMM based timing, and area optimization for their designs. Results and comparisons from case studies will be presented in the session

SUITE SESSION Physical verification (PV) complexity continues to grow by leaps and bounds as customers move to the advanced nodes that require multi-patterning. Come learn about the emerging trends in PV and how the Calibre nmPlatform continues to rapidly expand, addressing the needs for advanced PV and helping you get your design to market faster.

SUITE SESSION Silicon photonics is using silicon for the fabrication of light-based devices—such as lasers, amplifiers, converters, filters and splitters. Current applications include ultra-fast chip-to-chip optical interconnects, optical routers and signal processors. Visionaries see SP as an enabling technology that will impact many facets of life through entertainment, medical discovery, communications, information storage, and manufacturing. This session discusses the impact photonics will have on today’s IC design and manufacturing processes, the tool requirements for SP, foundry options, new applications that will SP open up, and new challenges it will present to IC designers.

SUITE SESSION Reliability issues usually require design verification driven from circuit schematics to the corresponding layout data. Traditional DRC engines can’t distinguish the specific functions of layout geometries, so manual markers are required to enable automated checks. However, erroneous markers can jeopardize reliability checking. Calibre PERC provides a fully automated and comprehensive EDA design platform to check ESD, latch-up, EOS, ERC and other design issues in both design and stream out databases. Calibre PERC is the first, and currently the only available tool with a qualified design kit from several major foundries for reliability signoff. In this session, to be presented in Mandarin, Mentor Graphics and Semiconductor Manufacturing International Corporation (SMIC) discuss reliability checking with Calibre PERC.

SUITE SESSION The infrastructure necessary for the realization of 3D-ICs continues to improve. Mentor now offers a wide set of test solutions for this growing segment. This presentation will provide an overview of these capabilities followed by a more detailed review of test solutions for memories vertically stacked on an interposer or logic die. These solutions support different memory interface protocols such as WideIO and DDR4 and are already being used by some Mentor customers.