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Monday, June 02

Monday, June 02

9:00 AM - 10:00 AM  2 sessions

Suite B
  • Custom IC Design and AMS Simulation/Verification – Unparalleled Insight and Productivity
    Toggle Abstract

    TECHNICAL SESSION From our complete Custom IC Design flow through our industry leading simulators and analog/ mixed-signal verification systems, Mentor solutions provide insight and productivity.  This session provides an overview of the analog/mixed-signal product portfolio with an emphasis on new capabilities, recent customer results, and a future vision.  We introduce the newest member of the portfolio, the Analog FastSPICE Platform from Berkeley Design Automation (BDA), now part of Mentor.

Presenter: Tom Daspit, Product Marketing Manager, Mentor Graphics
Products: Pyxis, Analog FastSPICE (AFS) Platform, Eldo, ADit
AMS/Custom IC Design
Suite C
  • Get Your FPGA Out of the Lab and into Production
    Toggle Abstract

    TECHNICAL SESSION Spending too much time in the Lab debugging your FPGA? FPGA’s have grown large and complex. So, too has the task of validating the functionality after it has passed all the tests for area, performance, and power. If there is a problem with your FPGA, where do you start looking? Combined with the powerful capabilities of the Mentor FPGA design flow spanning from design capture, implementation, and board design, come join us as we introduce new methods to not only produce better quality FPGA designs but also new methods and tools to help you instrument your FPGA design so that problems are easier to find as they happen.

Presenter: Jim Kenney, Marketing Director, Mentor Graphics
Products: HDL Designer, Precision, Questa
Design & Functional Verification

10:00 AM - 10:30 AM  1 session

Booth 1113
  • A New Era in Functional Verification
    Toggle Abstract

    TECHNICAL SESSION This special Verification Academy DAC session presents a historical perspective of functional verification—from transistors to systems. And then discusses a new era in functional verification with the emergence of functional verification solutions that address today’s unique SoC challenges.

Presenter: Harry Foster, Chief Verification Scientist, Mentor Graphics
Products: Questa
Verification Academy

10:00 AM - 11:00 AM  3 sessions

Suite A
  • Mentor RTL to GDS Digital Implementation for Best PPA at Advanced Nodes
    Toggle Abstract

    TECHNICAL SESSION Achieving best power, performance and area (PPA) has gotten significantly more difficult at advanced nodes (20/16nm and below) due to inherent challenges . At smaller nodes the traditional design closure flow is inadequate due to complex DRC and DFM rules, multi-patterning (MP) and FinFET requirements, growing design sizes, low power requirements, high performance targets and increasing process and design variations. This session will highlight some of the advanced Oasys RealTime Designer(tm) and Olympus-SoC(tm) technologies to achieve best PPA and efficient RTL-to-GDS design closure. We will focus on unique technologies such as MP and FinFET aware implementation, high capacity RTL synthesis, RTL floorplanning, concurrent PPA optimization for best QoR, and DRC/DP signoff during implementation.

Presenter: Arvind Narayanan, Product Marketing Manager, Integrated Circuit Implementation Division, Mentor Graphics
Presenter: Shankar Vellanthurai, Senior Product Engineer, Mentor Graphics
Products: IC Design & Test
IC Design & Test
Suite B
  • Update on DFM and Fill for Advanced Nodes
    Toggle Abstract

    TECHNICAL SESSION At 28 nm and below, litho process checking (LPC), CMP analysis and critical area analysis (CAA) are all crucial steps to help ensure manufacturability. In addition, layout fill has become a more complex and critical issue. Come to this session to understand today’s DFM issues, to find out what is required by the foundries at each node, to learn about updates to DFM tools, and to see how SmartFill is changing the approach to fill at advanced nodes.

Presenter: Jeff Wilson, DFM Product Marketing Manager, Mentor Graphics
Presenter: Joe Kwan, Foundries Program Manager, Mentor Graphics
Products: Calibre LFD, Calibre YieldEnhancer, Calibre YieldAnalyzer
IC Design & Test
Suite C
  • Full SoC Emulation from Device Drivers to Peripheral Interfaces
    Toggle Abstract

    TECHNICAL SESSION Companies have added a tape out requirement that ensures their SoC executes the OS loader to a boot prompt. Thus, verification of HW/SW interactions is no longer just a good idea, it’s a hard requirement. The methods for executing and debugging OS boot and device driver software on hardware during emulation are evolving rapidly. This session contrasts live versus off-line SW debug tools in the context of multi-core SoC designs, and physical versus virtual peripheral models as device driver targets. Participants will come away with an understanding of how an emulation-based, end-to-end flow yields a higher confidence at tape out and a faster time to market.

Products: Veloce
Design & Functional Verification

11:00 AM - 11:30 AM  1 session

Booth 1113
  • Power exploration to RTL power convergence for advanced designs
    Toggle Abstract

    TECHNICAL SESSION Because over 80% of the final SoC/IP power is decided at the RT level, designers need to explore multiple power intent options and converge on power goals prior to place and route.  This presentation will discuss how Questa-Power Aware and Calypto PowerPro enables users to accurately analyze various power intent choices and then optimize for best power reduction at RTL without losing any functionality.

Presenter: Anand Iyer, Product Marketing, Calypto
Products: Questa
Verification Academy

11:00 AM - 12:00 PM  3 sessions

Suite A
  • Parasitic Extraction to Meet the Challenge of Advanced Nodes
    Toggle Abstract

    TECHNICAL SESSION The world is 3D! Leading edge designers are considering new designs at advanced process nodes with 3D transistors (FinFETs). Others are considering “More than Moore” and opting for a 3D-IC approach. Everyone wants more accuracy which implies 3D modeling techniques to achieve high correlation against reference results. With these new challenges come traditional concerns of turn-around time (TAT), growing design complexity, double-patterning and growing number of interconnect corners that add to the challenge of robust parasitic extraction. This session will describe how new methods in Calibre have been developed to address these challenges and meet the performance, accuracy, and usability concerns for designers at all nodes.

Presenter: Carey Robertson, Director of Product Marketing, LVS and Extraction, Mentor Graphics
Products: Calibre nmLVS, Calibre xACT
IC Design & Test
Suite B
  • Better Layout in Less Time: AMD’s Experience with Calibre RealTime at 20nm and Below
    Toggle Abstract

    TECHNICAL SESSION Physical implementation is significantly more challenging at 20nm than at previous nodes. Introducing Calibre RealTime into the production flow at AMD enabled designers to meet this challenge and improve the quality of the layout at the same time. Calibre RealTime provides immediate feedback for implementation and the ability to optimize the layout with full sign-off feedback. This enables us to make last-minute edits with sign-off confidence, and to reduce the number of batch DRC iterations required to reach tape-out.

Presenter: Kalyan Chakravarthy, Member of Technical Staff, AMD
Presenter: Srinivas Velivala, Calibre TME, Mentor Graphics
Products: Calibre RealTime
IC Design & Test
Suite C
  • Questa: High-Performance Simulation, Emulation and much more
    Toggle Abstract

    TECHNICAL SESSION With the growing size, complexity and software content of today’s SoC designs, verification requires a platform that gives you more than just simulation. Come see how Questa ties simulation, formal and emulation together and brings testbench automation, coverage closure, low power, abstract portable stimulus, new system-level metrics and more to maximizes your verification productivity.

Presenter: Steve Bailey, Director of Emerging Technologies, Mentor Graphics
Products: Veloce, Questa
Design & Functional Verification

1:00 PM - 2:00 PM  3 sessions

Suite A
  • PyxisOpen — Assisted Automation for the Toughest Custom IC Design Problems
    Toggle Abstract

    TECHNICAL SESSION Mentor is bringing revolutionary insight and automation to the most intensively manual portion of custom IC design with PyxisOpen’s new OpenAccess (OA) based automation core. Learn how our interactive custom router boosts productivity as it shortens routing time by 10X and cuts weeks off tapeout schedules. See a demo of our OA-based automation core and Calibre RealTime integration. 

Presenter: Tom Daspit, Product Marketing Manager, Mentor Graphics
Products: PyxisOpen
AMS/Custom IC Design
Suite B
  • Introduction to the Analog FastSPICE (AFS) Platform
    Toggle Abstract

    TECHNICAL SESSION The latest addition to the Mentor analog/mixed-signal simulation and verification family is the Analog FastSPICE (AFS) Platform developed by Berkeley Design Automation (BDA), now part of Mentor. This session provides details on the AFS Platform, the world’s fastest circuit verification for nanometer analog, RF, mixed-signal, and custom digital circuits. Foundry certified to 16nm/14nm FinFET-based processes, the AFS Platform delivers nanometer SPICE accuracy 5x-10x faster than traditional SPICE and 2x-6x faster than parallel SPICE simulators. For large analog/mixed-signal circuits, the AFS Platform delivers greater than 10M-element capacity and the fastest mixed-signal simulation. For silicon-accurate characterization, it includes the industry’s only full-spectrum, device noise analysis and delivers near-linear performance scaling with the number of cores. Come hear what Analog FastSPICE can do for your analog/mixed-signal design and verification flow.

Presenter: Mick Tegethoff, Product Marketing Manager, Mentor Graphics
Products: Analog FastSPICE (AFS) Platform
AMS/Custom IC Design
Suite C
  • Innovative Virtual Prototype Technologies for System and Application Bring-up
    Toggle Abstract

    TECHNICAL SESSION Traditional embedded system design is transforming to a new world of Virtual embedded software and hardware design. Mentor’s virtual prototyping solution is revolutionizing embedded platform-based design by enabling debug of hardware/software complex interactions and by providing analysis capabilities not achievable with traditional simulation or on prototyping boards. It offers a tightly coupled HW/SW debug, analysis and verification capabilities that are changing the traditional design paradigm on prototyping boards. This includes observing the behaviour of the platform’s software in a non-intrusive manner, without introducing any observation effects. This session will illustrate the level of control, visibility and analysis capabilities available on a reference virtual prototype to guide efficient software and hardware development that meets the functionality and performance goals.

Presenter: Shabtay Matalon, Market Development Manager, Mentor Graphics
Products: Vista, CodeBench-Virtual Edition
Design & Functional Verification

2:00 PM - 2:30 PM  1 session

Booth 1113
  • UVM Transactions - Important Undocumented Details
    Toggle Abstract

    TECHNICAL SESSION Fundamental questions most novice UVM users ponder include: Why uses classes instead of structs to define transactions for verification environments? What are advantages of using classes to represent transactions in a verification environment? Do I have to define different input and output classes for UVM testbenches? Why do I have to use do_methods() or field macros to override standard transaction methods? Why don't I just override the transaction methods directly? How do do_methods() and field macros work? SystemVerilog Guru and UVM expert, Cliff Cummings, will answer these questions and more to clarify many important details about UVM transactions.

Presenter: Cliff Cummings, President, Sunburst Design
Products: Questa
Verification Academy

2:00 PM - 3:00 PM  3 sessions

Suite A
  • Improving Circuit Reliability with Calibre PERC
    Toggle Abstract

    TECHNICAL SESSION Circuit reliability continues to be a focus for all process nodes. Verification techniques that extend beyond traditional DRC, LVS and ERC checks are needed to meet the demands of today’s designs. Device and interconnect reliability solutions that are scalable across many designs without the need for manual intervention improves the repeatability and efficiency of these checks. Come see how we leverage unique technology with foundry-provided rule decks to solve some of the most challenging reliability concerns IC designers face. We will also discuss electrical overstress (EOS), current density and electromigration issues, to name a few, which can be solved by the comprehensive Calibre PERC reliability verification platform.

Presenter: Matt Hogan, Product Marketing Manager, Calibre Design Solutions, Mentor Graphics
Products: Calibre PERC
IC Design & Test
Suite B
  • Test Solutions for High-Quality Automotive Devices
    Toggle Abstract

    TECHNICAL SESSION The growing amount of electronics within today’s automobiles is driving very high quality and reliability requirements to a widening range of semiconductor devices. Improvements in test solutions are needed not only to maintain very high quality levels in more advanced technology nodes but to also address increasing reliability requirements such as defined within the ISO 26262 standard. New test approaches to be described will include a new hybrid ATPG compression and logic BIST solution that provides more efficient defect coverage together with the ability to apply tests within the system for long-term reliability. This hybrid solution also supports a new cell-aware test generation approach that has been shown to significantly reduce DPM levels in shipped devices.

Presenter: Steve Pateras, Product Marketing Director, Silicon Test Products, Mentor Graphics
Products: Tessent
IC Design & Test
Suite C
  • How to Accelerate Verification with 5 Easy to Use Formal Apps
    Toggle Abstract

    TECHNICAL SESSION What if you could harness the benefits of formal verification without the pain? That’s exactly what Questa’s fully-automatic formal apps allow you to do. This session presents the top 5 apps used to get better quality designs out the door faster. We’ll review apps for: (1) Clock-domain crossings, (2) Common RTL coding errors, (3) X-states, (4) Coverage closure, (5) Property generation.

Presenter: Roger Sabbagh, Product Marketing Manager, Mentor Graphics
Products: Questa
Design & Functional Verification

3:00 PM - 3:30 PM  1 session

Booth 1113
  • UVM: What’s New, What’s Next, and Why You Care
    Toggle Abstract

    TECHNICAL SESSION You may have heard there’s a new version of UVM that’s recently been released. This session will teach you everything you need to know about the future of UVM. We’ll briefly cover the new features included in UVM1.2 and how to minimize their impact, and we’ll identify the key subset of UVM features that will make your environment truly reusable from block to system-level verification while providing the ideal platform for integrating new solutions and standards.

Presenter: Tom Fitzpatrick, Verification Technologist, Mentor Graphics
Products: Questa
Verification Academy

3:00 PM - 4:00 PM  2 sessions

Suite A
  • Mentor RTL to GDS Digital Implementation for Best PPA at Advanced Nodes
    Toggle Abstract

    TECHNICAL SESSION Achieving best power, performance and area (PPA) has gotten significantly more difficult at advanced nodes (20/16nm and below) due to inherent challenges . At smaller nodes the traditional design closure flow is inadequate due to complex DRC and DFM rules, multi-patterning (MP) and FinFET requirements, growing design sizes, low power requirements, high performance targets and increasing process and design variations. This session will highlight some of the advanced Oasys RealTime Designer(tm) and Olympus-SoC(tm) technologies to achieve best PPA and efficient RTL-to-GDS design closure. We will focus on unique technologies such as MP and FinFET aware implementation, high capacity RTL synthesis, RTL floorplanning, concurrent PPA optimization for best QoR, and DRC/DP signoff during implementation.

Presenter: Arvind Narayanan, Product Marketing Manager, Integrated Circuit Implementation Division, Mentor Graphics
Presenter: Shankar Vellanthurai, Senior Product Engineer, Mentor Graphics
Products: Olympus-SoC, Oasys RealTime Designer
IC Design & Test
Suite C
  • Visualizer: A Powerful Debug Environment for Complex SOCs
    Toggle Abstract

    TECHNICAL SESSION This session will focus on improving debug productivity with Visualizer, Mentor’s NEW high performance and capacity debug environment. Visualizer is tightly integrated with both Questa simulation and Veloce emulation to improve debug productivity for RTL, gates and SV/UVM testbenches. Visualizer is fast and intuitive with powerful, automated features that help pinpoint the cause of errors and explore your design.

Presenter: Anissa Mawer, Verification Technology Manager, Mentor Graphics
Products: Veloce, Questa, Visualizer
Design & Functional Verification

4:00 PM - 5:00 PM  2 sessions

Booth 1733
  • Back to the Future: Is There Success without Moore's Law?
    Toggle Abstract

    PANEL There seems to be a lot of angst in the industry over the increasing costs of extending IC scalability. For decades, the success of our industry has been predicated on Moore’s Law—the ability to deliver exponentially increasing logic density at continuously decreasing costs. Can the industry be successful without this virtuous cycle? The reality is that many players are doing very well without pushing the leading edge of scalability. This panel will look at the ways that IC innovators are adding value to established IC nodes through increasing functionality, reduced power consumption, higher reliability, integration of MEMS and silicon photonics, and die stacking. Come and pick up some new ideas from our panel while you’re enjoying Happy Hour at the Mentor booth.

Presenter: Michael Buehler-Garcia, Senior Director of Marketing for Calibre Design Solutions, Mentor Graphics
Products: Calibre
IC Design & Test
Suite C
  • 100% Verified But the Chip Failed – Why?
    Toggle Abstract

    TECHNICAL SESSION You reached 100% coverage on your chip so why did it still fail? The problem may lie within your design process. Design flaws found late in the design cycle or, even worse, in the field or production, are not only costly, but could pose safety risks.  Mentor’s solution starts at the beginning – with the design requirements. Not verifying to the requirements can result in untested or incorrectly implemented aspects of the design. This session walks you through a repeatable requirements validation approach to verify 100% to the requirements.

Presenter: Valerie Rachko, Marketing Director, Mentor Graphics
Products: ReqTracer, HDL Designer
Design & Functional Verification

Tuesday, June 03

Tuesday, June 03

9:00 AM - 9:30 AM  1 session

Booth 1113
  • How off-the-shelf IP can cut time spent on PCIe verification in half
    Toggle Abstract

    TECHNICAL SESSION The presentation will highlight how PLDA, built a PCIe UVM/SystemVerilog-based verification environment and how the work reduced time spent on verification by a factor of two compared to PLDA’s previous Verilog/SystemVerilog-based environment.

Presenter: Romain Tourneau, PLDA
Products: Questa
Verification Academy

9:00 AM - 10:00 AM  2 sessions

Suite B
  • Custom IC Design and AMS Simulation/Verification – Unparalleled Insight and Productivity
    Toggle Abstract

    TECHNICAL SESSION From our complete Custom IC Design flow through our industry leading simulators and analog/ mixed-signal verification systems, Mentor solutions provide insight and productivity.  This session provides an overview of the analog/mixed-signal product portfolio with an emphasis on new capabilities, recent customer results, and a future vision.  We introduce the newest member of the portfolio, the Analog FastSPICE Platform from Berkeley Design Automation (BDA), now part of Mentor.

Presenter: Tom Daspit, Product Marketing Manager, Mentor Graphics
Products: Pyxis, Analog FastSPICE (AFS) Platform, Eldo, ADit
AMS/Custom IC Design
Suite C
  • Get Your FPGA Out of the Lab and into Production
    Toggle Abstract

    TECHNICAL SESSION Spending too much time in the Lab debugging your FPGA? FPGA’s have grown large and complex. So, too has the task of validating the functionality after it has passed all the tests for area, performance, and power. If there is a problem with your FPGA, where do you start looking? Combined with the powerful capabilities of the Mentor FPGA design flow spanning from design capture, implementation, and board design, come join us as we introduce new methods to not only produce better quality FPGA designs but also new methods and tools to help you instrument your FPGA design so that problems are easier to find as they happen.

Presenter: Jim Kenney, Marketing Director, Mentor Graphics
Products: HDL Designer, Precision, Questa
Design & Functional Verification

10:00 AM - 10:30 AM  1 session

Booth 1113
  • A New Era in Functional Verification
    Toggle Abstract

    TECHNICAL SESSION This special Verification Academy DAC session presents a historical perspective of functional verification—from transistors to systems. And then discusses a new era in functional verification with the emergence of functional verification solutions that address today’s unique SoC challenges.

Presenter: Harry Foster, Chief Verification Scientist, Mentor Graphics
Products: Questa
Verification Academy

10:00 AM - 11:00 AM  3 sessions

Suite A
  • Mentor RTL to GDS Digital Implementation for Best PPA at Advanced Nodes
    Toggle Abstract

    TECHNICAL SESSION Achieving best power, performance and area (PPA) has gotten significantly more difficult at advanced nodes (20/16nm and below) due to inherent challenges . At smaller nodes the traditional design closure flow is inadequate due to complex DRC and DFM rules, multi-patterning (MP) and FinFET requirements, growing design sizes, low power requirements, high performance targets and increasing process and design variations. This session will highlight some of the advanced Oasys RealTime Designer(tm) and Olympus-SoC(tm) technologies to achieve best PPA and efficient RTL-to-GDS design closure. We will focus on unique technologies such as MP and FinFET aware implementation, high capacity RTL synthesis, RTL floorplanning, concurrent PPA optimization for best QoR, and DRC/DP signoff during implementation.

Presenter: Arvind Narayanan, Product Marketing Manager, Integrated Circuit Implementation Division, Mentor Graphics
Presenter: Shankar Vellanthurai, Senior Product Engineer, Mentor Graphics
Products: Olympus-SoC, Oasys RealTime Designer
IC Design & Test
Suite B
  • Update on DFM and Fill for Advanced Nodes
    Toggle Abstract

    TECHNICAL SESSION At 28 nm and below, litho process checking (LPC), CMP analysis and critical area analysis (CAA) are all crucial steps to help ensure manufacturability. In addition, layout fill has become a more complex and critical issue. Come to this session to understand today’s DFM issues, to find out what is required by the foundries at each node, to learn about updates to DFM tools, and to see how SmartFill is changing the approach to fill at advanced nodes.

Presenter: Jeff Wilson, DFM Product Marketing Manager, Mentor Graphics
Presenter: Joe Kwan, Foundries Program Manager, Mentor Graphics
Products: Calibre LFD, Calibre YieldEnhancer, Calibre YieldAnalyzer
IC Design & Test
Suite C
  • Full SoC Emulation from Device Drivers to Peripheral Interfaces
    Toggle Abstract

    TECHNICAL SESSION Companies have added a tape out requirement that ensures their SoC executes the OS loader to a boot prompt. Thus, verification of HW/SW interactions is no longer just a good idea, it’s a hard requirement. The methods for executing and debugging OS boot and device driver software on hardware during emulation are evolving rapidly. This session contrasts live versus off-line SW debug tools in the context of multi-core SoC designs, and physical versus virtual peripheral models as device driver targets. Participants will come away with an understanding of how an emulation-based, end-to-end flow yields a higher confidence at tape out and a faster time to market.

Products: Veloce
Design & Functional Verification

10:30 AM - 12:00 PM  2 sessions

Room 303
  • On Timing Closure: Buffer Insertion for Hold-Violation Removal F
    Toggle Abstract

    TECHNICAL PAPER This session discusses some key challenges in timing closure and future generation physical design. The first two papers specifically discuss physical challenges of 3D ICs in terms of design methodologies, performance and packaging while the remaining papers present new techniques and algorithms for timing closure of high-performance designs.

Presenter: Ivailo Nedelchev, Chief Technologist, Mentor Graphics
Presenter: Sarvesh Bhardwaj, Lead Engineer, Mentor Graphics
Presenter: Vidyamani Parkhe, IC Architect, Mentor Graphics
Products: Calibre
IC Design & Test
Room 303
  • On Using Implied Values in EDT-Based Test Compression F
    Toggle Abstract

    TECHNICAL PAPER If process variations, defects or test costs keep you up at night, this is your chance to face your demons. This session introduces novel test methods to uncover defects, diagnosis strategies to pinpoint failure root-cause and calibration techniques to compensate for manufacturing imperfections.

Presenter: Grzegorz Mrugalski, SW Development Manager, Mentor Graphics
Presenter: Janusz Rajski, Development Engineer Director, Mentor Graphics
Presenter: Nilanjan Mukherjee, Development Engineer Director, Mentor Graphics
Products: Calibre
IC Design & Test

11:00 AM - 11:30 AM  1 session

Booth 1113
  • Verification and Debug: Old School Meets New School
    Toggle Abstract

    TECHNICAL SESSION “Old school” debug typically involves applying vectors directly to the design, a level of self-checking and then exploring the design with source, waves, and others to figure out what went wrong. With “new school” verification methodologies (UVM, randomization, golden reference models) the debug techniques need to be expanded. This session covers how you use the best of both worlds to find problems faster and to better answer “if you are done yet”.

Presenter: Rich Edelman, Verification Architect, Mentor Graphics
Products: Questa
Verification Academy

11:00 AM - 11:45 AM  1 session

Booth 313
  • Fireside Chat: Automotive Engineers Love Design Automation F
    Toggle Abstract

    PANEL Having heard the exciting and informative keynote in the formal setting, come to the Pavilion for an informal interaction with James Buczkowski as Wally Rhines engages him in a wide ranging conversation from his career and cars of the future to designing for safety and the role of EDA in his world. Be prepared to ask your own questions such as why the nifty feature everyone wants in their car is missing, or if a driverless flying car will ever be available for the masses?

Presenter: Walden Rhines, Chairman and Chief Executive Officer, Mentor Graphics
Products: Automotive
Automotive

11:00 AM - 12:00 PM  3 sessions

Suite B
  • Samsung Ecosystem Collaboration with Mentor for DFM at 14nm and Below
    Toggle Abstract

    TECHNICAL SESSION For the 14nm node, Mentor and Samsung have collaborated extensively to create a comprehensive DFM solution that includes proven solutions for litho simulation, pattern matching, critical area analysis (CAA) and advanced filling. Come to this session to understand what was done and how it can help you move to 14nm.

Presenter: Jean-Marie Brunet, Product Marketing Director for Design for Manufacturing (DFM) and Place & Route Integration, Mentor Graphics
Presenter: Kuang-Kuo Lin, Director of Foundry Design Enablement at America Headquarters Device Solutions, Samsung Semiconductor
Products: Calibre LFD, Calibre YieldEnhancer, Calibre YieldAnalyzer
IC Design & Test
Suite A
  • Calibre Advanced Physical Verification: Learn What’s Coming Your Way at 16/14nm and 10nm and How Calibre is Already Prepared
    Toggle Abstract

    TECHNICAL SESSION Physical verification (PV) complexity continues to grow by leaps and bounds as customers move to the advanced nodes that require multi-patterning and more recently FinFETs. Come learn about the emerging trends in PV and how the Calibre nmPlatform continues to rapidly expand, addressing the needs for advanced PV and helping you get your design to market faster.

Presenter: Michael White, Director of Product Marketing, Calibre Physical Verification Products, Mentor Graphics
Products: Calibre nmDRC
IC Design & Test
Suite C
  • Questa: High-Performance Simulation, Emulation and much more
    Toggle Abstract

    TECHNICAL SESSION With the growing size, complexity and software content of today’s SoC designs, verification requires a platform that gives you more than just simulation. Come see how Questa ties simulation, formal and emulation together and brings testbench automation, coverage closure, low power, abstract portable stimulus, new system-level metrics and more to maximizes your verification productivity.

Presenter: Steve Bailey, Director of Emerging Technologies, Mentor Graphics
Products: Veloce, Questa
Design & Functional Verification

1:00 PM - 2:00 PM  2 sessions

Suite A
  • Not Jumping to 16/14nm Tomorrow? Extend the Lifetime and Get the Most Out of Established Nodes with Advanced Calibre
    Toggle Abstract

    TECHNICAL SESSION With the costs and complexity of 20nm and below, customers are staying longer at established nodes (e.g. 90nm – 28nm). They are also pushing much more complex designs through these nodes than ever before. Come learn how Calibre has solutions to help you get the most out of established processes for your next design.

Presenter: John Ferguson, Director of Marketing, Calibre DRC Applications, Mentor Graphics
Products: Calibre nmDRC
IC Design & Test
Suite C
  • Innovative Virtual Prototype Technologies for System and Application Bring-up
    Toggle Abstract

    TECHNICAL SESSION Traditional embedded system design is transforming to a new world of Virtual embedded software and hardware design. Mentor’s virtual prototyping solution is revolutionizing embedded platform-based design by enabling debug of hardware/software complex interactions and by providing analysis capabilities not achievable with traditional simulation or on prototyping boards. It offers a tightly coupled HW/SW debug, analysis and verification capabilities that are changing the traditional design paradigm on prototyping boards. This includes observing the behaviour of the platform’s software in a non-intrusive manner, without introducing any observation effects. This session will illustrate the level of control, visibility and analysis capabilities available on a reference virtual prototype to guide efficient software and hardware development that meets the functionality and performance goals.

Presenter: Shabtay Matalon, Market Development Manager, Mentor Graphics
Products: Vista, CodeBench-Virtual Edition
Design & Functional Verification

1:30 PM - 3:00 PM  2 sessions

Room 310
  • Applying EDA Techniques to Analysis and Optimization to In-vehicle Distributed Systems F
    Toggle Abstract

    TECHNICAL SESSION Modern vehicles have complex architectures with many electronic control units (ECUs) and different communication buses that are used to implement different distributed control algorithms. Developing such complex hardware/software systems rely on building accurate virtual prototypes ad simulators, which are used both for systems design & optimization, as well as for parallel software development. This session will feature different talks discussing various challenges and solutions in this domain.

Presenter: Serge Leef, VP New Ventures, GM System-Level Engineering Division, Mentor Graphics
Products: Automotive
Automotive
Room 300
  • Fast and Accurate Full-chip Extraction and Optimization of TSV-to-Wire Coupling F
    Toggle Abstract

    TECHNICAL PAPER This session covers topics from transistor-level to circuit-level modeling in 2D and 3D IC designs.

Presenter: Dusan Petranovic, Technical Marketing Engineer, Mentor Graphics
Products: Calibre
IC Design & Test

2:00 PM - 3:00 PM  3 sessions

Suite B
  • Better Layout in Less Time: AMD’s Experience with Calibre RealTime at 20nm and Below
    Toggle Abstract

    TECHNICAL SESSION Physical implementation is significantly more challenging at 20nm than at previous nodes. Introducing Calibre RealTime into the production flow at AMD enabled designers to meet this challenge and improve the quality of the layout at the same time. Calibre RealTime provides immediate feedback for implementation and the ability to optimize the layout with full sign-off feedback. This enables us to make last-minute edits with sign-off confidence, and to reduce the number of batch DRC iterations required to reach tape-out.

Presenter: Kalyan Chakravarthy, Member of Technical Staff, AMD
Presenter: Srinivas Velivala, Calibre TME, Mentor Graphics
Products: Calibre RealTime
IC Design & Test
Suite A
  • The Challenges of Power Grid Design in Advanced ICs
    Toggle Abstract

    TECHNICAL SESSION Power analysis has assumed a much more important and demanding role in the IC design flow. Exploding design sizes and complexity combined with a host of new analysis requirements has made this a very challenging design task. Designers need to analyze the impact of IR drop and current in-rush on signal integrity, current density and electro-migration impact on reliability, and other power-related issues. This session will review current issues with power analysis and discuss the capabilities needed to address them.

Presenter: Christen Decoin, Product Marketing Manager for New and Emerging Markets, Mentor Graphics
Products: Calibre
IC Design & Test
Suite C
  • How to Accelerate Verification with 5 Easy to Use Formal Apps
    Toggle Abstract

    TECHNICAL SESSION What if you could harness the benefits of formal verification without the pain? That’s exactly what Questa’s fully-automatic formal apps allow you to do. This session presents the top 5 apps used to get better quality designs out the door faster. We’ll review apps for: (1) Clock-domain crossings, (2) Common RTL coding errors, (3) X-states, (4) Coverage closure, (5) Property generation.

Presenter: Roger Sabbagh, Product Marketing Manager, Mentor Graphics
Products: Questa
Design & Functional Verification

2:30 PM - 3:00 PM  1 session

Booth 1113
  • Achieving Broad & Flexible Debug Visibility if FPGA Prototypes
    Toggle Abstract

    TECHNICAL SESSION A key challenge in using FPGA prototypes is debugging, specifically in hardware or the interaction of software and hardware. Although many organizations have developed homegrown hardware instruments, silicon debug visibility continues to challenge the productive use of FPGA prototypes as a verification engine. Debugging system-level interactions driven by software sequences requires the ability to capture traces over a long period of time.This sessions discusses a solution that combines resource-efficient embedded instruments that dramatically increase visibility with software to provide a very flexible, easy-to-use silicon debug solution.

Presenter: Steve Bailey, Director of Emerging Technologies, Mentor Graphics
Products: Questa
Verification Academy

3:00 PM - 3:30 PM  1 session

Booth 1113
  • UVM: What’s New, What’s Next, and Why You Care
    Toggle Abstract

    TECHNICAL SESSION You may have heard there’s a new version of UVM that’s recently been released. This session will teach you everything you need to know about the future of UVM. We’ll briefly cover the new features included in UVM1.2 and how to minimize their impact, and we’ll identify the key subset of UVM features that will make your environment truly reusable from block to system-level verification while providing the ideal platform for integrating new solutions and standards.

Presenter: Tom Fitzpatrick, Verification Technologist, Mentor Graphics
Products: Questa
Verification Academy

3:00 PM - 4:00 PM  3 sessions

Suite A
  • Mentor RTL to GDS Digital Implementation for Best PPA at Advanced Nodes
    Toggle Abstract

    TECHNICAL SESSION Achieving best power, performance and area (PPA) has gotten significantly more difficult at advanced nodes (20/16nm and below) due to inherent challenges . At smaller nodes the traditional design closure flow is inadequate due to complex DRC and DFM rules, multi-patterning (MP) and FinFET requirements, growing design sizes, low power requirements, high performance targets and increasing process and design variations. This session will highlight some of the advanced Oasys RealTime Designer(tm) and Olympus-SoC(tm) technologies to achieve best PPA and efficient RTL-to-GDS design closure. We will focus on unique technologies such as MP and FinFET aware implementation, high capacity RTL synthesis, RTL floorplanning, concurrent PPA optimization for best QoR, and DRC/DP signoff during implementation.

Presenter: Arvind Narayanan, Product Marketing Manager, Integrated Circuit Implementation Division, Mentor Graphics
Presenter: Shankar Vellanthurai, Senior Product Engineer, Mentor Graphics
Products: Olympus-SoC, Oasys RealTime Designer
IC Design & Test
Suite B
  • Tessent Support of ARM Cores and Memories_x000D_
    Toggle Abstract

    TECHNICAL SESSION Mentor Graphics and ARM are partnering to provide customers with tools to deliver the most advanced, defect free and highest yielding IC products to market in a timely manner. The two companies continue to work to ensure Mentor’s Tessent family of silicon test products are optimized to provide comprehensive and cost-effective test coverage of ARM processors and memory IP. This presentation will describe test solutions developed to cover both the memory and logic test requirements of ARM-based designs. Special emphasis will be placed on the automated support of the ARM standardized MBIST (aka Shared Bus) core interface. This interface enables test access to memories through the functional path, resulting in higher quality test and reduced impact on performance.

Presenter: Steve Pateras, Product Marketing Director, Silicon Test Products, Mentor Graphics
Products: Tessent
IC Design & Test
Suite C
  • Visualizer: A Powerful Debug Environment for Complex SOCs
    Toggle Abstract

    TECHNICAL SESSION This session will focus on improving debug productivity with Visualizer, Mentor’s NEW high performance and capacity debug environment. Visualizer is tightly integrated with both Questa simulation and Veloce emulation to improve debug productivity for RTL, gates and SV/UVM testbenches. Visualizer is fast and intuitive with powerful, automated features that help pinpoint the cause of errors and explore your design.

Presenter: Anissa Mawer, Verification Technology Manager, Mentor Graphics
Products: Veloce, Questa, Visualizer
Design & Functional Verification

4:00 PM - 4:30 PM  1 session

Booth 1113
  • Maximize Verification Reuse with Portable Stimulus
    Toggle Abstract

    TECHNICAL SESSION Verification productivity and reuse are of key concern when verifying today’s complex designs. The ability to rapidly create large amounts of comprehensive test sequences at block, subsystem, SoC and system level are key to ensuring design quality. One key obstacle to achieving comprehensive testing today is the lack of a consistent stimulus specification that is reusable from block to system level. Recently, in response to industry demand, the Accellera Systems Initiative board launched a proposed working group to investigate whether to standardize a portable stimulus specification. This session will show how a portable stimulus specification brings 10-100x faster coverage closure to block level verification, and reusable comprehensive tests to SoC and system level verification

Presenter: Matthew Balance, Verification Technologist, Mentor Graphics
Products: Questa
Verification Academy

4:00 PM - 5:00 PM  4 sessions

Booth 1733
  • What will Moore's Law Cost Us at 10nm?
    Toggle Abstract

    PANEL For the first time in many years, there is a lot of uncertainty about how we get to the next IC scaling nodes. Will EUV be ready? Will we have to go to triple or quadruple patterning? Can DSA be commercialized quickly enough? What are the cost implications for these various alternatives? Can we see a way to get to 10nm and 7nm with an affordable technology? Are we at the point where designs are so tightly linked to a manufacturer’s specific process that multi-sourcing is unfeasible? How much commonality is there, and what can tools do to hide the differences? If it’s doable, is multi-sourcing economically viable? This panel will consider these all important questions and provide some insights if not the final answers. Be prepared for a wide open discussion and some big differences of opinion. Come and get engaged in the discussion while you’re enjoying Happy Hour at the Mentor booth.

Presenter: Joe Sawicki, Vice President and General Manager Design to Silicon Division, Mentor Graphics
Products: Calibre
IC Design & Test
Suite A
  • PyxisOpen — Assisted Automation for the Toughest Custom IC Design Problems
    Toggle Abstract

    TECHNICAL SESSION Mentor is bringing revolutionary insight and automation to the most intensively manual portion of custom IC design with PyxisOpen’s new OpenAccess (OA) based automation core. Learn how our interactive custom router boosts productivity as it shortens routing time by 10X and cuts weeks off tapeout schedules. See a demo of our OA-based automation core and Calibre RealTime integration. 

Presenter: Tom Daspit, Product Marketing Manager, Mentor Graphics
Products: PyxisOpen
AMS/Custom IC Design
Suite B
  • Introduction to the Analog FastSPICE (AFS) Platform
    Toggle Abstract

    TECHNICAL SESSION The latest addition to the Mentor analog/mixed-signal simulation and verification family is the Analog FastSPICE (AFS) Platform developed by Berkeley Design Automation (BDA), now part of Mentor. This session provides details on the AFS Platform, the world’s fastest circuit verification for nanometer analog, RF, mixed-signal, and custom digital circuits. Foundry certified to 16nm/14nm FinFET-based processes, the AFS Platform delivers nanometer SPICE accuracy 5x-10x faster than traditional SPICE and 2x-6x faster than parallel SPICE simulators. For large analog/mixed-signal circuits, the AFS Platform delivers greater than 10M-element capacity and the fastest mixed-signal simulation. For silicon-accurate characterization, it includes the industry’s only full-spectrum, device noise analysis and delivers near-linear performance scaling with the number of cores. Come hear what Analog FastSPICE can do for your analog/mixed-signal design and verification flow.

Presenter: Mick Tegethoff, Product Marketing Manager, Mentor Graphics
Products: Analog FastSPICE (AFS) Platform
AMS/Custom IC Design
Suite C
  • 100% Verified But the Chip Failed – Why?
    Toggle Abstract

    TECHNICAL SESSION You reached 100% coverage on your chip so why did it still fail? The problem may lie within your design process. Design flaws found late in the design cycle or, even worse, in the field or production, are not only costly, but could pose safety risks.  Mentor’s solution starts at the beginning – with the design requirements. Not verifying to the requirements can result in untested or incorrectly implemented aspects of the design. This session walks you through a repeatable requirements validation approach to verify 100% to the requirements.

Presenter: Valerie Rachko, Marketing Director, Mentor Graphics
Products: ReqTracer, HDL Designer
Design & Functional Verification

4:00 PM - 5:30 PM  1 session

Room 306
  • End-User Applications - Tests for Nothing and Verification for Free F
    Toggle Abstract

    PANEL To verify an IP one can create new tests  or extract IP-level tests from existing application software. So far, verification teams have been creating new tests for each new IP. While highly efficient tests can be created , the process is time consuming. The alternative of test extraction is inefficient. But, what if the process of extracting IP-level tests from application software were automated?  A large trove of tests would be readily available even before a new IP development began. One camp believes that extraction  is an old idea: it never has worked because it is not efficient. Another camp believes that today this is possibly the only way to complete verification on time. Who holds the winning approach?

Presenter: Harry Foster, Chief Verification Scientist, Mentor Graphics
Products: Questa
Design & Functional Verification

4:00 PM - 6:00 PM  1 session

Room 105
  • Power Aware Clock Domain Crossing Verification F
    Toggle Abstract

    TECHNICAL SESSION Formal and static methods, which analyze a design directly rather than depending on large numbers of simulation vectors, are becoming increasingly important in the world of modern design. In the first part of this session, real-world practitioners who have been successful with formal verification describe case studies and use them to supply useful advice for those who wish to achieve similar results. Then we move on to describe some new and powerful uses for static and formal techniques in conjunction with other tools and methods, providing new insights into IP integration, clock domain crossings, power issues, and clock/reset design.

Presenter: Roger Sabbagh, Product Marketing Manager, Mentor Graphics
Presenter: Saumitra Goel, Lead Consultant Staff, Mentor Graphics
Products: Questa
Design & Functional Verification

Wednesday, June 04

Wednesday, June 04

9:00 AM - 10:00 AM  2 sessions

Suite B
  • Custom IC Design and AMS Simulation/Verification – Unparalleled Insight and Productivity
    Toggle Abstract

    TECHNICAL SESSION From our complete Custom IC Design flow through our industry leading simulators and analog/ mixed-signal verification systems, Mentor solutions provide insight and productivity.  This session provides an overview of the analog/mixed-signal product portfolio with an emphasis on new capabilities, recent customer results, and a future vision.  We introduce the newest member of the portfolio, the Analog FastSPICE Platform from Berkeley Design Automation (BDA), now part of Mentor.

Presenter: Tom Daspit, Product Marketing Manager, Mentor Graphics
Products: Pyxis, Analog FastSPICE (AFS) Platform, Eldo, ADit
AMS/Custom IC Design
Suite C
  • Get Your FPGA Out of the Lab and into Production
    Toggle Abstract

    TECHNICAL SESSION Spending too much time in the Lab debugging your FPGA? FPGA’s have grown large and complex. So, too has the task of validating the functionality after it has passed all the tests for area, performance, and power. If there is a problem with your FPGA, where do you start looking? Combined with the powerful capabilities of the Mentor FPGA design flow spanning from design capture, implementation, and board design, come join us as we introduce new methods to not only produce better quality FPGA designs but also new methods and tools to help you instrument your FPGA design so that problems are easier to find as they happen.

Presenter: Jim Kenney, Marketing Director, Mentor Graphics
Products: HDL Designer, Precision, Questa
Design & Functional Verification

10:00 AM - 10:30 AM  1 session

Booth 1113
  • A New Era in Functional Verification
    Toggle Abstract

    TECHNICAL SESSION This special Verification Academy DAC session presents a historical perspective of functional verification—from transistors to systems. And then discusses a new era in functional verification with the emergence of functional verification solutions that address today’s unique SoC challenges.

Presenter: Harry Foster, Chief Verification Scientist, Mentor Graphics
Products: Questa
Verification Academy

10:00 AM - 11:00 AM  3 sessions

Suite A
  • Mentor RTL to GDS Digital Implementation for Best PPA at Advanced Nodes
    Toggle Abstract

    TECHNICAL SESSION Achieving best power, performance and area (PPA) has gotten significantly more difficult at advanced nodes (20/16nm and below) due to inherent challenges . At smaller nodes the traditional design closure flow is inadequate due to complex DRC and DFM rules, multi-patterning (MP) and FinFET requirements, growing design sizes, low power requirements, high performance targets and increasing process and design variations. This session will highlight some of the advanced Oasys RealTime Designer(tm) and Olympus-SoC(tm) technologies to achieve best PPA and efficient RTL-to-GDS design closure. We will focus on unique technologies such as MP and FinFET aware implementation, high capacity RTL synthesis, RTL floorplanning, concurrent PPA optimization for best QoR, and DRC/DP signoff during implementation.

Presenter: Arvind Narayanan, Product Marketing Manager, Integrated Circuit Implementation Division, Mentor Graphics
Presenter: Shankar Vellanthurai, Senior Product Engineer, Mentor Graphics
Products: Olympus-SoC, Oasys RealTime Designer
IC Design & Test
Suite B
  • Update on DFM and Fill for Advanced Nodes
    Toggle Abstract

    TECHNICAL SESSION At 28 nm and below, litho process checking (LPC), CMP analysis and critical area analysis (CAA) are all crucial steps to help ensure manufacturability. In addition, layout fill has become a more complex and critical issue. Come to this session to understand today’s DFM issues, to find out what is required by the foundries at each node, to learn about updates to DFM tools, and to see how SmartFill is changing the approach to fill at advanced nodes.

Presenter: Jeff Wilson, DFM Product Marketing Manager, Mentor Graphics
Presenter: Joe Kwan, Foundries Program Manager, Mentor Graphics
Products: Calibre LFD, Calibre YieldEnhancer, Calibre YieldAnalyzer
IC Design & Test
Suite C
  • Full SoC Emulation from Device Drivers to Peripheral Interfaces
    Toggle Abstract

    TECHNICAL SESSION Companies have added a tape out requirement that ensures their SoC executes the OS loader to a boot prompt. Thus, verification of HW/SW interactions is no longer just a good idea, it’s a hard requirement. The methods for executing and debugging OS boot and device driver software on hardware during emulation are evolving rapidly. This session contrasts live versus off-line SW debug tools in the context of multi-core SoC designs, and physical versus virtual peripheral models as device driver targets. Participants will come away with an understanding of how an emulation-based, end-to-end flow yields a higher confidence at tape out and a faster time to market.

Products: Veloce
Design & Functional Verification

11:00 AM - 11:30 AM  1 session

Booth 1113
  • Formal Verification Signoff Methodology
    Toggle Abstract

    TECHNICAL SESSION Formal sign-off is a relatively new concept in the industry. Like simulation sign-off, it requires a thorough and systematic methodology. This includes: end-to-end checkers, constraints, abstraction models and coverage points. This talk discusses each component of the formal sign-off methodology so that formal can be applied in the verification sign-off flow to maximize efficiency & productivity.

Presenter: Vigyan Singhal, President and CEO, Oski
Products: Questa
Verification Academy

11:00 AM - 12:00 PM  3 sessions

Suite A
  • Parasitic Extraction to Meet the Challenge of Advanced Nodes
    Toggle Abstract

    TECHNICAL SESSION The world is 3D! Leading edge designers are considering new designs at advanced process nodes with 3D transistors (FinFETs). Others are considering “More than Moore” and opting for a 3D-IC approach. Everyone wants more accuracy which implies 3D modeling techniques to achieve high correlation against reference results. With these new challenges come traditional concerns of turn-around time (TAT), growing design complexity, double-patterning and growing number of interconnect corners that add to the challenge of robust parasitic extraction. This session will describe how new methods in Calibre have been developed to address these challenges and meet the performance, accuracy, and usability concerns for designers at all nodes.

Presenter: Carey Robertson, Director of Product Marketing, LVS and Extraction, Mentor Graphics
Products: Calibre nmLVS, Calibre xACT
IC Design & Test
Suite B
  • Improving Circuit Reliability with Calibre PERC
    Toggle Abstract

    TECHNICAL SESSION Circuit reliability continues to be a focus for all process nodes. Verification techniques that extend beyond traditional DRC, LVS and ERC checks are needed to meet the demands of today’s designs. Device and interconnect reliability solutions that are scalable across many designs without the need for manual intervention improves the repeatability and efficiency of these checks. Come see how we leverage unique technology with foundry-provided rule decks to solve some of the most challenging reliability concerns IC designers face. We will also discuss electrical overstress (EOS), current density and electromigration issues, to name a few, which can be solved by the comprehensive Calibre PERC reliability verification platform.

Presenter: Matt Hogan, Product Marketing Manager, Calibre Design Solutions, Mentor Graphics
Products: Calibre PERC
IC Design & Test
Suite C
  • Questa: High-Performance Simulation, Emulation and much more
    Toggle Abstract

    TECHNICAL SESSION With the growing size, complexity and software content of today’s SoC designs, verification requires a platform that gives you more than just simulation. Come see how Questa ties simulation, formal and emulation together and brings testbench automation, coverage closure, low power, abstract portable stimulus, new system-level metrics and more to maximizes your verification productivity.

Presenter: Steve Bailey, Director of Emerging Technologies, Mentor Graphics
Products: Veloce, Questa
Design & Functional Verification

1:00 PM - 2:00 PM  3 sessions

Suite A
  • PyxisOpen — Assisted Automation for the Toughest Custom IC Design Problems
    Toggle Abstract

    TECHNICAL SESSION Mentor is bringing revolutionary insight and automation to the most intensively manual portion of custom IC design with PyxisOpen’s new OpenAccess (OA) based automation core. Learn how our interactive custom router boosts productivity as it shortens routing time by 10X and cuts weeks off tapeout schedules. See a demo of our OA-based automation core and Calibre RealTime integration. 

Presenter: Tom Daspit, Product Marketing Manager, Mentor Graphics
Products: PyxisOpen
AMS/Custom IC Design
Suite B
  • Introduction to the Analog FastSPICE (AFS) Platform
    Toggle Abstract

    TECHNICAL SESSION The latest addition to the Mentor analog/mixed-signal simulation and verification family is the Analog FastSPICE (AFS) Platform developed by Berkeley Design Automation (BDA), now part of Mentor. This session provides details on the AFS Platform, the world’s fastest circuit verification for nanometer analog, RF, mixed-signal, and custom digital circuits. Foundry certified to 16nm/14nm FinFET-based processes, the AFS Platform delivers nanometer SPICE accuracy 5x-10x faster than traditional SPICE and 2x-6x faster than parallel SPICE simulators. For large analog/mixed-signal circuits, the AFS Platform delivers greater than 10M-element capacity and the fastest mixed-signal simulation. For silicon-accurate characterization, it includes the industry’s only full-spectrum, device noise analysis and delivers near-linear performance scaling with the number of cores. Come hear what Analog FastSPICE can do for your analog/mixed-signal design and verification flow.

Presenter: Mick Tegethoff, Product Marketing Manager, Mentor Graphics
Products: Analog FastSPICE (AFS) Platform
AMS/Custom IC Design
Suite C
  • Innovative Virtual Prototype Technologies for System and Application Bring-up
    Toggle Abstract

    TECHNICAL SESSION Traditional embedded system design is transforming to a new world of Virtual embedded software and hardware design. Mentor’s virtual prototyping solution is revolutionizing embedded platform-based design by enabling debug of hardware/software complex interactions and by providing analysis capabilities not achievable with traditional simulation or on prototyping boards. It offers a tightly coupled HW/SW debug, analysis and verification capabilities that are changing the traditional design paradigm on prototyping boards. This includes observing the behaviour of the platform’s software in a non-intrusive manner, without introducing any observation effects. This session will illustrate the level of control, visibility and analysis capabilities available on a reference virtual prototype to guide efficient software and hardware development that meets the functionality and performance goals.

Presenter: Shabtay Matalon, Market Development Manager, Mentor Graphics
Products: Vista, CodeBench-Virtual Edition
Design & Functional Verification

1:30 PM - 2:30 PM  1 session

Room 306
  • FinFET and IC Design: Mountain or Mole Hill? F
    Toggle Abstract

    PANEL FinFETs have moved from the industry roadmap into industry deployment. The test chips are back. Many designs are underway. The 14nm process is being projected to tighter rules that will bring even more concerns about FIN gate performance, depending on many factors such as sidewall and FIN characteristics, including pitches and height to mention some. The pressing questions from many are: how big of a deal are FinFETs to my design process? How is the EDA industry responding to design needs to predict the impact of the FIN parameters in device performance, reliability and manufacturability in general?

Presenter: Jean-Marie Brunet, Product Marketing Director for Design for Manufacturing (DFM) and Place & Route Integration, Mentor Graphics
Products: Calibre
IC Design & Test

1:30 PM - 3:00 PM  1 session

Room 310
  • Connected Engineering for Automtive EE Design F
    Toggle Abstract

    TECHNICAL SESSION A well managed process with seamless information flow from concept to design to verification to in-production updating (e.g. software updates) is the holy grail for a fully enabled Systems Engineering process. Aspects of this enablement is the theme of this session and it looks at three different views of how systems engineering is enabled at various levels in the process.

Presenter: Joachim Langenwalter, Director, Automotive, Europe, Mentor Graphics
Products: Automotive
Automotive

2:00 PM - 3:00 PM  2 sessions

Suite A
  • The Challenges of Power Grid Design in Advanced ICs
    Toggle Abstract

    TECHNICAL SESSION Power analysis has assumed a much more important and demanding role in the IC design flow. Exploding design sizes and complexity combined with a host of new analysis requirements has made this a very challenging design task. Designers need to analyze the impact of IR drop and current in-rush on signal integrity, current density and electro-migration impact on reliability, and other power-related issues. This session will review current issues with power analysis and discuss the capabilities needed to address them.

Presenter: Marko Chew, Technical Marketing Engineer, Mentor Graphics
Products: Calibre
IC Design & Test
Suite C
  • How to Accelerate Verification with 5 Easy to Use Formal Apps
    Toggle Abstract

    TECHNICAL SESSION What if you could harness the benefits of formal verification without the pain? That’s exactly what Questa’s fully-automatic formal apps allow you to do. This session presents the top 5 apps used to get better quality designs out the door faster. We’ll review apps for: (1) Clock-domain crossings, (2) Common RTL coding errors, (3) X-states, (4) Coverage closure, (5) Property generation.

Presenter: Roger Sabbagh, Product Marketing Manager, Mentor Graphics
Products: Questa
Design & Functional Verification

3:00 PM - 3:30 PM  1 session

Booth 1113
  • Instant Formal Expert
    Toggle Abstract

    TECHNICAL SESSION Formal sign-off is a relatively new concept in the industry. Like simulation sign-off, it requires a thorough and systematic methodology. This includes: end-to-end checkers, constraints, abstraction models and coverage points. This talk discusses each component of the formal sign-off methodology so that formal can be applied in the verification sign-off flow to maximize efficiency & productivity.

Presenter: Jeremy Levitt, Engineering Manager, Mentor Graphics
Products: Questa
Verification Academy

3:00 PM - 4:00 PM  2 sessions

Suite A
  • Mentor RTL to GDS Digital Implementation for Best PPA at Advanced Nodes
    Toggle Abstract

    TECHNICAL SESSION Achieving best power, performance and area (PPA) has gotten significantly more difficult at advanced nodes (20/16nm and below) due to inherent challenges . At smaller nodes the traditional design closure flow is inadequate due to complex DRC and DFM rules, multi-patterning (MP) and FinFET requirements, growing design sizes, low power requirements, high performance targets and increasing process and design variations. This session will highlight some of the advanced Oasys RealTime Designer(tm) and Olympus-SoC(tm) technologies to achieve best PPA and efficient RTL-to-GDS design closure. We will focus on unique technologies such as MP and FinFET aware implementation, high capacity RTL synthesis, RTL floorplanning, concurrent PPA optimization for best QoR, and DRC/DP signoff during implementation.

Presenter: Arvind Narayanan, Product Marketing Manager, Integrated Circuit Implementation Division, Mentor Graphics
Presenter: Shankar Vellanthurai, Senior Product Engineer, Mentor Graphics
Products: Olympus-SoC, Oasys RealTime Designer
IC Design & Test
Suite C
  • Visualizer: A Powerful Debug Environment for Complex SOCs
    Toggle Abstract

    TECHNICAL SESSION This session will focus on improving debug productivity with Visualizer, Mentor’s NEW high performance and capacity debug environment. Visualizer is tightly integrated with both Questa simulation and Veloce emulation to improve debug productivity for RTL, gates and SV/UVM testbenches. Visualizer is fast and intuitive with powerful, automated features that help pinpoint the cause of errors and explore your design.

Presenter: Anissa Mawer, Verification Technology Manager, Mentor Graphics
Products: Veloce, Questa, Visualizer
Design & Functional Verification

4:00 PM - 5:00 PM  2 sessions

Booth 1733
  • Tackling FinFET Analog Mixed Signal and Memory Verification
    Toggle Abstract

    PANEL Analog, mixed-signal, and SRAM design teams migrating to FinFET process nodes are implementing new architectures to take advantage of FinFET benefits and overcome its limitations. As a result they need to retool their transistor-level verification flow for more accuracy, performance and capacity to offset the increased layout, device modeling, device noise, voltage scaling, and process variation effects. Designers of complex analog/mixed-signal circuits such as PLLs, ADCs, SerDes, and transceivers, need to explore alternative architectures and measure their impact in non-planar silicon. Embedded SRAM design teams realize that it is no longer acceptable to tolerate 5% or more inaccuracy in memory IP characterization. This panel is an interactive forum where attendees can exchange ideas and questions with a group of experts who are tackling the exciting opportunities and challenges related to the move to FinFET nodes.

Presenter: Ravi Subramanian, General Manager, AMS, Mentor Graphics
Products: Analog Mixed Signal
AMS/Custom IC Design
Suite C
  • 100% Verified But the Chip Failed – Why?
    Toggle Abstract

    TECHNICAL SESSION You reached 100% coverage on your chip so why did it still fail? The problem may lie within your design process. Design flaws found late in the design cycle or, even worse, in the field or production, are not only costly, but could pose safety risks.  Mentor’s solution starts at the beginning – with the design requirements. Not verifying to the requirements can result in untested or incorrectly implemented aspects of the design. This session walks you through a repeatable requirements validation approach to verify 100% to the requirements.

Presenter: Valerie Rachko, Marketing Director, Mentor Graphics
Products: ReqTracer, HDL Designer
Design & Functional Verification

4:00 PM - 5:30 PM  1 session

Room 306
  • Is Model-Driven Development the Answer to Design Complexity? F
    Toggle Abstract

    PANEL The challenge of increased complexity in the development of next-generation embedded and cyberphysical systems is still to be solved. Many different solutions are being proposed, targeting a subset of multiple domains that must be integrated together depending on the starting design point, including physical, mathematical, digital, electronics and software. Different types of tools are competing on the market, all promising to solve the problem of modeling cyberphysical systems. Model-driven development, heterogeneous system modeling frameworks, prototyping frameworks: what is the best methodology?

Presenter: Serge Leef, VP New Ventures, GM System-Level Engineering Division, Mentor Graphics
Products: Embedded Software
Embedded Software

6:00 PM - 7:00 PM  7 sessions

Esplanade Foyer 
  • Stress Assessment for Device Performance in 3D IC F
Presenter: Armen Kteyan, Lead Engineer, Mentor Graphics
Presenter: Gevorg Gevorgyan, Engineer, Mentor Graphics
Presenter: Henrik Hovsepyan, R&D Manager, Mentor Graphics
Presenter: Jun-Ho Choy, Engineer, Mentor Graphics
Presenter: Valeriy Sukharev, Principle Engineer, Mentor Graphics
Products: Calibre
IC Design & Test
Esplanade Foyer 
  • Geometric Pattern Match Using Edge Driven Dissected Rectangles and Vector Space F
Presenter: Robert Todd, Chief Engineering Scientist, Mentor Graphics
Products: Calibre
IC Design & Test
Esplanade Foyer 
  • New Trends in TSV: SWCNT-Based TSV and Air-Gap Based Coaxial TSV F
Presenter: Khaled Mohamed, Technical Engineer, Mentor Graphics
Products: Calibre
IC Design & Test
Esplanade Foyer 
  • Physical Verification of Hierarchical Analog Design Constraints for Automotive ICs F
Presenter: Dina Medhat, Senior Technical Marketing Engineer, Mentor Graphics
Presenter: Hartmut Marquardt, Senior Application Engineer, Mentor Graphics
Products: Calibre
IC Design & Test
Esplanade Foyer 
  • Advanced Layout Reliability Verification Methodology For Mixed Signal and Multi-Power Domain Designs F
Presenter: Jen Chen, Senior Application Engineer, Mentor Graphics
Presenter: Sridhar Srinivasan, R&D Staff Engineer, Mentor Graphics
Presenter: Srinivas Velivala, Calibre TME, Mentor Graphics
Products: Calibre
IC Design & Test
Esplanade Foyer 
  • Modeling Proximity-Induced Variability in Standard Cells for Optimized Timing Performance F
Presenter: Mohamed Dessouky, Engineer, Mentor Graphics
Presenter: Mohamed Said, Senior IC Design Consultant, Mentor Graphics
Products: Calibre
IC Design & Test
Esplanade Foyer 
  • A Novel Dimensional Analysis Method for TSV Modeling and Analysis in Three Dimensional Integrated Circuits F
Presenter: Khaled Mohamed, Technical Engineer, Mentor Graphics
Products: Calibre
IC Design & Test