All Mentor@DAC Events

SUITE SESSION One of the predominant place and route challenges is realizing best power, performance and area (PPA), a goal that has gotten significantly more difficult to achieve at advanced nodes (20nm and below). At smaller technology nodes the traditional design closure flow is inadequate due to complex DRC / DFM rules, double patterning requirements, growing design sizes, low power requirements and increasing process and design variations. In addition to solving these challenges, it is also critical to achieve high utilization and reduce the die size to justify the cost of moving to smaller nodes. This session will highlight some of the advanced Olympus-SoC technologies to achieve efficient design closure with unique technologies such as concurrent PPA optimization, pseudo flat flow methodology and DRC/DP signoff during implementation.

SUITE SESSION Reliability issues usually require design verification driven from circuit schematics to the corresponding layout data. Traditional DRC engines can’t distinguish the specific functions of layout geometries, so manual markers are required to enable automated checks. However, erroneous markers can jeopardize reliability checking. Calibre PERC provides a fully automated and comprehensive EDA design platform to check ESD, latch-up, EOS, ERC and other design issues in both design and stream out databases. Calibre PERC is the first, and currently the only available tool with a qualified design kit from several major foundries for reliability signoff. In this session, to be presented in Mandarin, Mentor Graphics and Semiconductor Manufacturing International Corporation (SMIC) discuss reliability checking with Calibre PERC. Mon 10:00 in Mentor booth.

SUITE SESSION Every two years, Mentor Graphics commissions Wilson Research Group conducts a broad, vendor-independent survey of design verification practices around the world. This presentation reveals the results of this just-completed study—and the observed convergence of SoC design practices toward a common methodology.

KEYNOTE To commemorate the conference's 50th anniversary, DAC has invited key leaders in the electronic industry to present 8 to 10 minute visionary talks before each of the Keynote address. Visionary Talks will disperse an incredible variety of inspiring, visionary ideas. Each industry leader speaking has brought something innovative and integral to the industry. Join us before each keynote to explore the challenging new ideas and innovative thinking of the leaders that have helped shaped our industry and hear where they think the next 50 years will bring us.

PARTNER KIOSK PRESENTATION Successful IC manufacturing at 20nm requires some important design optimization strategies. Fill becomes much more sophisticated because it’s no longer just about planarity, but a whole range of interrelated effects, such as etch, lithography, stress, and rapid thermal annealing (RTA). Verification of latch-up immunity depends on automated measurements and analysis, for example, determining the resistance of paths in output driver arrays as a function of device spacing. Other circuit checks address reliability issues, including electrostatic discharge (ESD), electrical overstress (EOS), and errors arising from signals crossing multiple power domains. This session will highlight areas where Mentor and GLOBALFOUNDRIES have collaborated to deliver solutions to new design enabling challenges. Mon 10:45 in the GLOBALFOUNDRIES booth.

SUITE SESSION At 28 nm and below, litho process checking (LPC), CMP analysis and critical area analysis (CAA) are all crucial steps to help ensure manufacturability. In addition, layout fill has become a more complex and critical issue. While in the past the goal was simply to insert minimum fill to maintain planarity, today you need to maximize fill and place and orient it precisely to optimize its benefits. Come to this session to understand today’s DFM issues, to find out what is required by the foundries at each node, to learn about updates to DFM tools, and to see how SmartFill is changing the approach to fill at advanced nodes.

SUITE SESSION ISO 26262 is emerging as a standard that’s being rapidly adopted by the automotive industry. This standard specifies objectives that must be met in the development of safety critical automotive electronics systems. This standard is already starting to push new requirements down to the semiconductor suppliers for these automotive subsystems. This is creating an opportunity for automotive semiconductor suppliers to differentiate themselves based on their test strategy, which can make their offering more appealing for ISO 26262 mandated systems. This session will focus on features and solutions within Mentor Graphics’ Tessent silicon test and yield analysis products that can be leveraged for designs destined for an ISO 26262 application.

SUITE SESSION Microchip has been doing low power verification with UPF and Questa PASim for several years. Their devices contain multiple power domains, a substantial amount of analog circuitry and different behaviors whether “in the wall” or “on battery” and with different voltage levels: all must be verified. This sessions describes their low power challenges, methodology, and flow from RTL to GLS.

SUITE SESSION The Veloce hardware emulation system tackles the two primary aspects of power during system-level verification. Power aware verification ensures that power management logic and software control were implemented correctly and that the power functionality of the design is correct. Power analysis identifies activity peaks and drives data to 3rd party power estimation tools. In this session, we will look at both aspects of designing for power and discuss how they can be used independently or collectively for system-level verification.

WORKSHOP In this tutorial, we will present the evolution of an OpenGL ES application development and execution flow across software and hardware threads and through virtual and physical embedded hardware targets. The entire flow is driven with a unified native Software IDE with embedded hardware visibility and profiling features.

The tutorial will delve into all aspects of software-driven debugging and optimization while migrating from a pure virtual prototype target, and software rendering implementation across to graphical processing engine executing on an emulator or a physical board.

The real-world impact of the flow described in this tutorial is far reaching. Graphical applications such as visual computing, image processing and 3D animation and navigation are a fundamental component of many modern mobile, automotive and gaming devices.

SUITE SESSION The parasitic extraction flow is being challenged on a number of fronts: the need for higher accuracy at smaller dimensions, the complexity of high transistor and gate counts and more extensive fill, the impact of double patterning on modeling and accuracy, the need for new models for FinFETs and Through Silicon Via (TSVs), and the need to handle ECOs in an fast and efficient manner. This session will describe these new challenges and also new approaches to PEX that can deliver the required capabilities while significantly reducing turnaround time.

SUITE SESSION In this session STMicroelectronics will be sharing their experience and successes in using Olympus-SoC on their designs. They will be specifically covering the key backend design challenges and how Olympus was effectively used for timing and design closure including MCMM based timing, and area optimization for their designs. Results and comparisons from case studies will be presented in the session

SUITE SESSION In the world of ever increasing verification complexity, is anything getting any easier? For some good news on this front, join us for this session where we will examine solutions which add automation to the verification process. Focus areas include: reset and X-state propagation, enhanced coverage through automatic property generation, handling the convergence of multiple clock and power domains, and more!

SUITE SESSION A new revision of UPF, IEEE 1801-2013 UPF, also known as UPF 2.1, has just been approved. UPF 2.1 clarifies and enhances many of the capabilities of UPF 2.0, as well as adding some new features to enable power intent specifications for more complex designs. This session presents an overview of the changes in UPF 2.1 and explains how these refinements and new features will make power intent specification easier.

SUITE SESSION When leading edge customers first transitioned to 20nm they encountered issues not experienced in prior nodes with the set-up of hardware, flows, and use models during chip verification. TSMC and Mentor worked with these customers to resolve the issues resulting in successful tape-outs of these customers’ designs. TSMC and Mentor will present best practices learned from that experience to help other customers smoothly tape-out their advanced process node designs. Mon 2:00, Mentor booth.

SUITE SESSION Implementing a robust IC verification methodology that addresses circuit reliability is increasingly difficulty for all process nodes. Larger nodes are seeing new challenges that were not apparent in previous generations, such as increasing design complexity. Smaller nodes are seeing greater sensitivity to electrical overstress (EOS), current density and electro-migration issues. For designs with multiple complex power domains, transistor-level power intent verification can be difficult to verify, but new tools are emerging to automate such checking by leveraging UPF. This session describes how Calibre PERC can provide a comprehensive reliability verification platform to address these problems.

SUITE SESSION This presentation will show how Model Driven Development can address common challenges in the system design, verification & testing of complex systems and systems of systems. Project success requires that hardware, software and test teams fluently integrate application software, controlling firmware, analog and digital hardware, and mechanical components. Successfully integrating and verifying such a complex multi-disciplinary system often proves to be costly in terms of time, money, and engineering resources. This presentation covers the Model Driven Development of a virtual prototype that supports system engineering teams along with software, digital hardware, analog hardware, system interconnect algorithm development, hardware / software co-simulation and virtual system integration using a tools flow emphasizing requirements tracing, UML system modeling, and linking to functional FPGA, IC and PCB domains.

SUITE SESSION For Cypress PSOC devices, the lowest possible power consumption with very short design cycles is critical. Validating the power management (multiple power domains, power up/down of individual blocks) early in the design cycle is key. This session describes the Cypress UPF-based methodology using Questa PASim that helped find and debug power bugs at RTL that would have been disastrous late in the design cycle.

WORKSHOP In this tutorial, we will present the evolution of an OpenGL ES application development and execution flow across software and hardware threads and through virtual and physical embedded hardware targets. The entire flow is driven with a unified native Software IDE with embedded hardware visibility and profiling features.

The tutorial will delve into all aspects of software-driven debugging and optimization while migrating from a pure virtual prototype target, and software rendering implementation across to graphical processing engine executing on an emulator or a physical board.

The real-world impact of the flow described in this tutorial is far reaching. Graphical applications such as visual computing, image processing and 3D animation and navigation are a fundamental component of many modern mobile, automotive and gaming devices.

PARTNER KIOSK PRESENTATION Mentor will describe advances to support TSMC's 20nm IC processes. Calibre has a new engine with DP anchoring and pre-coloring, DP design rule checking, voltage-dependent checking and patented real-time graphical “error rings” to simplify fixing DP violations. A new 20nm Calibre PERC deck addresses potential reliability issues such as ESD and latch-up. Calibre SmartFill optimizes filling while ensuring that overall run times and files sizes are controlled. The Calibre LFD™ product works with the TSMC Unified DFM Engine, incorporating Calibre Pattern Matching technology to accelerate the litho hot spot detection. Mon 2:30 in the TSMC booth.

SUITE SESSION Explore how the Kronos integrated platform for cell library characterization of standard cell, IO pad and complex cells reduces characterization time enabling complex flip-flops that would normally take 30 minutes to complete on a single machine in as little as one minute. Discuss how Kronos Analyzer can compare library correctness and automatically find cell maps between libraries based on cell behavior.

SUITE SESSION How can you verify twice as much as the last project, in the same amount of time, using the same amount of resource and the same team? This session will focus on what’s new in all areas of the Questa Platform (performance, debug, TB/stimulus creation, coverage closure, low power, SoC verification), and how the platform unifies and automates tools, engines, and methodology into adoptable solutions so that 1+1=3.

SUITE PANEL Several high growth IC markets are experiencing demand for higher reliability, including mobile/wireless, automotive, industrial control and medical. At the same time, factors such as thinner gate oxide and multiple power rails have the potential to introduce subtle design flaws leading to delayed failure mechanisms. This panel will be an interactive forum where experts and attendees on the show floor can discuss the demand for IC reliability, what design methodologies can reduce the occurrence of delayed failure mechanisms, and how design for reliability checks can be automated to help remove the burden from designers. The panel will be immediately followed by a hosted bar happy hour.

SUITE SESSION This session will look at proven applications of UVM to move you from the conceptual to the practical. We will explore how UVM provides the ideal infrastructure for adopting new techniques, tools and technologies to improve your verification effectiveness. In addition, we will show how the advanced technologies in Questa use UVM to expand your verification capabilities in ways you may not have even thought of.

PANEL The sheer volume of information needed to capture, model, verify, manufacture, and test an SoC is exploding. Challenges include increasing runtimes, data center costs, and sharing information securely across multiple locations. Learn about possible solutions: new design methodologies, cloud services, secure ecosystem networks, and more efficient data formats.

SUITE SESSION Today, FPGA design is not just writing HDL code, but getting the design to meet design goals and validating the complex functionality that has been implemented. There is no substitute for good coding style, but it’s not enough to get the best performance or area utilization results. Expert knowledge of the design tools is invaluable for maximizing results, but who has time to become a tool expert? Once the design goals are met and the FPGA is on the board, does it function as intended? Considerable time is being spent in the "lab" analyzing why a design does not work correctly. In this presentation, new technologies will be showcased in design exploration and validation. Tools should automatically help you get the best results, and rule out or find where possible errors can be introduced in your design between the HDL code and the actual physical implementation on the board. Learn how Mentor Graphics has automated design exploration and design validation processes to maximize your FPGA design effort.

SUITE SESSION With the explosion of portable electronic devices, designing for low-power is a critical design constraint. The RTL design phase provides the ideal opportunity to dramatically reduce power, since several micro-architectural transformations can be done at this stage, via automated tools or manually. This session will review how Power Analysis can be done at the RTL level to drive low power optimizations.

SUITE SESSION Mentor Graphics is bringing revolutionary insight and automation to the most manual portions of custom IC design – the core – routing, placement and floor planning. Hear how our revolutionary interactive custom router is changing the competitive game for its users as it shortens routing time by 10X’s and cuts weeks of our customer’s tape out schedules. Also enjoy a sneak preview of our next deliveries for the automation core.

SUITE SESSION Power has become a critical design constraint for today’s electronic systems. IEEE 1801 Unified Power Format (UPF) enables specification of power intent to drive both verification and implementation of electronic systems. This session introduces UPF concepts and commands for defining the power management architecture of a system and presents methodology for incorporating power intent into IP and systems design.

WORKSHOP In this tutorial, we will present the evolution of an OpenGL ES application development and execution flow across software and hardware threads and through virtual and physical embedded hardware targets. The entire flow is driven with a unified native Software IDE with embedded hardware visibility and profiling features.

The tutorial will delve into all aspects of software-driven debugging and optimization while migrating from a pure virtual prototype target, and software rendering implementation across to graphical processing engine executing on an emulator or a physical board.

The real-world impact of the flow described in this tutorial is far reaching. Graphical applications such as visual computing, image processing and 3D animation and navigation are a fundamental component of many modern mobile, automotive and gaming devices.

SUITE SESSION From our complete Custom IC Design flow through our industry leading simulators and analog Mixed Signal verification systems, Mentor Graphics solutions provide insight and productivity. This session will provide a quick overview of what is new across the product portfolio and then focus on the most recent customer results from our industry leading Faster SPICE simulator, Eldo Premier. Join us and learn about our new Electro-Thermal analysis features and how customers are gaining up to 12X performance improvement over traditional SPICE simulation.

SUITE SESSION At 28 nm and below, litho process checking (LPC), CMP analysis and critical area analysis (CAA) are all crucial steps to help ensure manufacturability. In addition, layout fill has become a more complex and critical issue. While in the past the goal was simply to insert minimum fill to maintain planarity, today you need to maximize fill and place and orient it precisely to optimize its benefits. Come to this session to understand today’s DFM issues, to find out what is required by the foundries at each node, to learn about updates to DFM tools, and to see how SmartFill is changing the approach to fill at advanced nodes.

PARTNER KIOSK PRESENTATION The ability to effectively identify yield limiting design feature is a key asset for foundries and fabless semiconductor companies. This presentation covers the result of a collaboration between Mentor Graphics and GLOBALFOUNDRIES to rapidly identify systematic defects and critical design features based on silicon data [1-4]. Layout-aware diagnosis identifies the location and classification of defects causing manufacturing test failures. Specialized statistical analysis coupled with design profiling data (such as critical feature analysis) then determines the root cause of yield loss and separates design and process induced defects. Tue 10:00 in the GLOBALFOUNDRIES booth.

SUITE SESSION The infrastructure necessary for the realization of 3D-ICs continues to improve. Mentor now offers a wide set of test solutions for this growing segment. This presentation will provide an overview of these capabilities followed by a more detailed review of test solutions for memories vertically stacked on an interposer or logic die. These solutions support different memory interface protocols such as WideIO and DDR4 and are already being used by some Mentor customers.

SUITE SESSION Every two years, Mentor Graphics commissions Wilson Research Group conducts a broad, vendor-independent survey of design verification practices around the world. This presentation reveals the results of this just-completed study—and the observed convergence of SoC design practices toward a common methodology.

PANEL As designs move to 20nm and 14nm, reliability issues have become increasingly complex. EM is now a critical design sign-off requirement. ESD failures can significantly degrade the yield. Wear out-related defects impact circuit margining and lifetime requirement for critical applications. This panel will discuss the reliability challenges and debate what would be the best ways for designers, foundries, and EDA vendors to define and develop advanced circuit checks and design sign-off at these advanced nodes.

PARTNER KIOSK PRESENTATION One of the predominant P&R challenges is realizing best power, performance and area (PPA), a goal that is more difficult to achieve at advanced nodes due to complex DRC / DFM rules, double patterning, growing design sizes, low power requirements and increasing process and design variations. It is also critical to reduce the die size to justify the cost of moving to smaller nodes. This session shows advanced technologies for efficient design closure such as concurrent PPA optimization, pseudo flat flow methodology and DRC/DP signoff during implementation. Tue 11:00 in the TSMC booth.

SUITE SESSION Ensuring correct functionality of a SoC requires a holistic approach. Through comprehensive easy-to-use verification components, automated & intelligent test solutions, and high performance verification engines, this session will walk you through the critical steps needed for your SoC; interconnect subsystem, processor subsystem, to peripherals and special function accelerator blocks.

SUITE SESSION One of the predominant place and route challenges is realizing best power, performance and area (PPA), a goal that has gotten significantly more difficult to achieve at advanced nodes (20nm and below). At smaller technology nodes the traditional design closure flow is inadequate due to complex DRC / DFM rules, double patterning requirements, growing design sizes, low power requirements and increasing process and design variations. In addition to solving these challenges, it is also critical to achieve high utilization and reduce the die size to justify the cost of moving to smaller nodes. This session will highlight some of the advanced Olympus-SoC technologies to achieve efficient design closure with unique technologies such as concurrent PPA optimization, pseudo flat flow methodology and DRC/DP signoff during implementation.

SUITE SESSION Physical verification (PV) complexity continues to grow by leaps and bounds as customers move to the advanced nodes that require multi-patterning. Come learn about the emerging trends in PV and how the Calibre nmPlatform continues to rapidly expand, addressing the needs for advanced PV and helping you get your design to market faster.

SUITE SESSION The Veloce hardware emulation system tackles the two primary aspects of power during system-level verification. Power aware verification ensures that power management logic and software control were implemented correctly and that the power functionality of the design is correct. Power analysis identifies activity peaks and drives data to 3rd party power estimation tools. In this session, we will look at both aspects of designing for power and discuss how they can be used independently or collectively for system-level verification.

SUITE SESSION The parasitic extraction flow is being challenged on a number of fronts: the need for higher accuracy at smaller dimensions, the complexity of high transistor and gate counts and more extensive fill, the impact of double patterning on modeling and accuracy, the need for new models for FinFETs and Through Silicon Via (TSVs), and the need to handle ECOs in an fast and efficient manner. This session will describe these new challenges and also new approaches to PEX that can deliver the required capabilities while significantly reducing turnaround time.

SUITE SESSION This session will present some of the verification practices needed for efficient validation and verification of ARM v8 family compute sub-systems. We will explore some practical approaches to verification challenges for reuse, scalability and integrating cache coherency systems and solutions. Tues. 13:00, Verifcation Academy booth.

SUITE SESSION Designing a quantum photonic imagers poses a unique challenge to the P&R designers due to the inherent nature of the stacked die interface. This technology has a high density of signal interfaces driven by Analog macros that pose a big challenge during P&R from both a floorplanning and routing perspective. This session will talk about the full netlist to GDS implementation of the photonic imager design done using Olympus. The session will also cover how Olympus was able to handle the unique design requirements specifically from a floorplanning and routing standpoint, and was able to successfully achieve design closure.

SUITE SESSION In the world of ever increasing verification complexity, is anything getting any easier? For some good news on this front, join us for this session where we will examine solutions which add automation to the verification process. Focus areas include: reset and X-state propagation, enhanced coverage through automatic property generation, handling the convergence of multiple clock and power domains, and more!

SUITE SESSION TowerJazz, the global specialty foundry leader, is now providing Calibre PERC rule decks that enable their customers to perform circuit reliability verification during signoff. TowerJazz provides highly customized electrostatic discharge (ESD) and power management circuit checks based on their specific manufacturing processes. Many of these checks have been automated for the first time by taking advantage of the Calibre PERC product’s unique ability to combine schematic (net list) and physical layout information, which goes beyond the scope of traditional LVS, DRC and ERC tools. This is a one-time, limited seating session for advanced Calibre users. Tue 2:00, Mentor booth.

SUITE SESSION This presentation will show how Model Driven Development can address common challenges in the system design, verification & testing of complex systems and systems of systems. Project success requires that hardware, software and test teams fluently integrate application software, controlling firmware, analog and digital hardware, and mechanical components. Successfully integrating and verifying such a complex multi-disciplinary system often proves to be costly in terms of time, money, and engineering resources. This presentation covers the Model Driven Development of a virtual prototype that supports system engineering teams along with software, digital hardware, analog hardware, system interconnect algorithm development, hardware / software co-simulation and virtual system integration using a tools flow emphasizing requirements tracing, UML system modeling, and linking to functional FPGA, IC and PCB domains.

SUITE SESSION Silicon photonics is using silicon for the fabrication of light-based devices—such as lasers, amplifiers, converters, filters and splitters. Current applications include ultra-fast chip-to-chip optical interconnects, optical routers and signal processors. Visionaries see SP as an enabling technology that will impact many facets of life through entertainment, medical discovery, communications, information storage, and manufacturing. This session discusses the impact photonics will have on today’s IC design and manufacturing processes, the tool requirements for SP, foundry options, new applications that will SP open up, and new challenges it will present to IC designers. Tue 2:00, Mentor booth.

SUITE SESSION Hardware emulation systems tackle the two primary aspects of power during system-level verification. Power aware verification ensures that power management logic and software control were implemented correctly and that the power functionality of the design is correct. Power analysis identifies activity peaks and drives data to 3rd party power estimation tools. In this session, we will look at both aspects of designing for power and discuss how they can be used independently or collectively for system-level verification

PARTNER KIOSK PRESENTATION One of the predominant P&R challenges is realizing best power, performance and area (PPA), a goal that is more difficult to achieve at advanced nodes due to complex DRC / DFM rules, double patterning, growing design sizes, low power requirements and increasing process and design variations. It is also critical to reduce the die size to justify the cost of moving to smaller nodes. This session shows advanced technologies for efficient design closure such as concurrent PPA optimization, pseudo flat flow methodology and DRC/DP signoff during implementation. Tue 2:05 in the GLOBALFOUNDRIES booth.

SUITE SESSION The design regulations for FPGAs and ASICs in commercial and military aircraft are some of the strictest to adhere to and for good reason – failure of electronics in commercial aircraft can have catastrophic results. While the commercial air industry has mandated the DO-254 hardware design standard, military aerospace companies are adopting design processes similar to DO-254, some even having their own auditors. By taking a design approach that is requirements-driven and well integrated for FPGA and ASIC design creation through device implementation, an excellent design process can be followed that will enable meeting the compliance needs of DO-254 and other such regulations, while also improving the project’s efficiency, productivity, predictability and final chip quality. This session will present advanced chip design methods and practices that are now essential for any mil/aero FPGA or ASIC design project.

SUITE SESSION Explore how the Kronos integrated platform for cell library characterization of standard cell, IO pad and complex cells reduces characterization time enabling complex flip-flops that would normally take 30 minutes to complete on a single machine in as little as one minute. Discuss how Kronos Analyzer can compare library correctness and automatically find cell maps between libraries based on cell behavior.

SUITE SESSION How can you verify twice as much as the last project, in the same amount of time, using the same amount of resource and the same team? This session will focus on what’s new in all areas of the Questa Platform (performance, debug, TB/stimulus creation, coverage closure, low power, SoC verification), and how the platform unifies and automates tools, engines, and methodology into adoptable solutions so that 1+1=3.

SUITE PANEL The IC industry will undergo significant changes as future growth is driven not just by traditional Moore’s Law scaling, but also by “More Than Moore” technologies including 3D-IC, MEMS and silicon photonics. As these technologies emerge from R&D into volume production, they will create new opportunities for IC designers to add value to products. They will also challenge designers to find a way to combine the strengths of these technologies and to marry them into a unified EDA flow. This panel will be an interactive forum where attendees on the exhibition floor can exchange ideas and questions with a group of experts who are already grappling with these exciting opportunities and challenges. The panel will be immediately followed by a hosted bar happy hour.

SUITE SESSION This session will look at proven applications of UVM to move you from the conceptual to the practical. We will explore how UVM provides the ideal infrastructure for adopting new techniques, tools and technologies to improve your verification effectiveness. In addition, we will show how the advanced technologies in Questa use UVM to expand your verification capabilities in ways you may not have even thought of.

SUITE SESSION Formal property checking increases design quality and shrinks project schedules. However, when it comes time to develop your verification plan, it can be difficult to separate formal verification fact from fiction. In this session, we examine some of the common misconceptions about formal verification that interfere with its successful use. We’ll debunk these myths and show you how to use strategies that work!

SUITE SESSION Complexities and quality requirements of FPGA and ASIC designs today are demanding new design approaches that start with creation. The level of design abstraction must now be raised above RTL in order to contribute an entire new dimension of benefits to design, especially for multi-core architectures. Raising the design description language up from RTL to electronic system level (ESL), which is TLM-based (transaction level modeling), enables more design to designed, explored, validated, and co-designed with corresponding software and firmware using virtual prototypes to result in faster design cycles, higher quality projects, and higher levels of hardware and software design assurance.

SUITE SESSION Today, FPGA design is not just writing HDL code, but getting the design to meet design goals and validating the complex functionality that has been implemented. There is no substitute for good coding style, but it’s not enough to get the best performance or area utilization results. Expert knowledge of the design tools is invaluable for maximizing results, but who has time to become a tool expert? Once the design goals are met and the FPGA is on the board, does it function as intended? Considerable time is being spent in the "lab" analyzing why a design does not work correctly. In this presentation, new technologies will be showcased in design exploration and validation. Tools should automatically help you get the best results, and rule out or find where possible errors can be introduced in your design between the HDL code and the actual physical implementation on the board. Learn how Mentor Graphics has automated design exploration and design validation processes to maximize your FPGA design effort.

SUITE SESSION Mentor Graphics is bringing revolutionary insight and automation to the most manual portions of custom IC design – the core – routing, placement and floor planning. Hear how our revolutionary interactive custom router is changing the competitive game for its users as it shortens routing time by 10X’s and cuts weeks of our customer’s tape out schedules. Also enjoy a sneak preview of our next deliveries for the automation core.

SUITE SESSION Implementing a robust IC verification methodology that addresses circuit reliability is increasingly difficulty for all process nodes. Larger nodes are seeing new challenges that were not apparent in previous generations, such as increasing design complexity. Smaller nodes are seeing greater sensitivity to electrical overstress (EOS), current density and electro-migration issues. For designs with multiple complex power domains, transistor-level power intent verification can be difficult to verify, but new tools are emerging to automate such checking by leveraging UPF. This session describes how Calibre PERC can provide a comprehensive reliability verification platform to address these problems.

SUITE SESSION From our complete Custom IC Design flow through our industry leading simulators and analog Mixed Signal verification systems, Mentor Graphics solutions provide insight and productivity. This session will provide a quick overview of what is new across the product portfolio and then focus on the most recent customer results from our industry leading Faster SPICE simulator, Eldo Premier. Join us and learn about our new Electro-Thermal analysis features and how customers are gaining up to 12X performance improvement over traditional SPICE simulation.

SUITE SESSION With the growing design sizes at advanced nodes, top level chip assembly and optimization is done  using abstracts without the full chip context. This is an highly iterative and manual process that can have a noticeable huge impact on design turn-around time and QoR. In this session we will discuss the chip assembly solution from Olympus-SoC P&R platfomr including key technologies such as top level concurrent MCMM optimization, Synchronous optimization for replicated partitions, top level clock tuning and layer promotion of critical nets for faster timing convergence and design closure.

SUITE SESSION Every two years, Mentor Graphics commissions Wilson Research Group conducts a broad, vendor-independent survey of design verification practices around the world. This presentation reveals the results of this just-completed study—and the observed convergence of SoC design practices toward a common methodology.

SUITE SESSION The parasitic extraction flow is being challenged on a number of fronts: the need for higher accuracy at smaller dimensions, the complexity of high transistor and gate counts and more extensive fill, the impact of double patterning on modeling and accuracy, the need for new models for FinFETs and Through Silicon Via (TSVs), and the need to handle ECOs in an fast and efficient manner. This session will describe these new challenges and also new approaches to PEX that can deliver the required capabilities while significantly reducing turnaround time.

SUITE SESSION Formal based technologies are used at Oracle to supplement simulation and boost the efficacy and efficiency of the verification process. Join us for this session as we examine some pragmatic applications of formal verification and the impact the results have had at Oracle on project quality and schedule.

SUITE SESSION One of the predominant place and route challenges is realizing best power, performance and area (PPA), a goal that has gotten significantly more difficult to achieve at advanced nodes (20nm and below). At smaller technology nodes the traditional design closure flow is inadequate due to complex DRC / DFM rules, double patterning requirements, growing design sizes, low power requirements and increasing process and design variations. In addition to solving these challenges, it is also critical to achieve high utilization and reduce the die size to justify the cost of moving to smaller nodes. This session will highlight some of the advanced Olympus-SoC technologies to achieve efficient design closure with unique technologies such as concurrent PPA optimization, pseudo flat flow methodology and DRC/DP signoff during implementation.

SUITE SESSION The Veloce hardware emulation system tackles the two primary aspects of power during system-level verification. Power aware verification ensures that power management logic and software control were implemented correctly and that the power functionality of the design is correct. Power analysis identifies activity peaks and drives data to 3rd party power estimation tools. In this session, we will look at both aspects of designing for power and discuss how they can be used independently or collectively for system-level verification.

SUITE SESSION SystemVerilog is the mainstay of modern design and verification. Many new language features have been added in the 2012 standard to promote more efficient design and improve verification. Get an update on new features like multiple class interface inheritance, soft constraints, complex coverpoint bin expressions, new discrete real modeling and more!

SUITE SESSION In the world of ever increasing verification complexity, is anything getting any easier? For some good news on this front, join us for this session where we will examine solutions which add automation to the verification process. Focus areas include: reset and X-state propagation, enhanced coverage through automatic property generation, handling the convergence of multiple clock and power domains, and more!

PARTNER KIOSK PRESENTATION 3D transistors, or FinFETs, exacerbate concerns about quality and reliability at 16nm and below. While there has already been a lot of research into the types of defects expected with FinFETs, characterizing these defect mechanisms is only the first step. We also need a methodology for generating test patterns that efficiently target these new defects. This session will describe the use of the cell-aware test approach to meet this test requirement. Wed 2:30 in the TSMC booth.

PARTNER KIOSK PRESENTATION 3D transistors, or FinFETs, exacerbate concerns about quality and reliability at 16nm and below. While there has already been a lot of research into the types of defects expected with FinFETs, characterizing these defect mechanisms is only the first step. We also need a methodology for generating test patterns that efficiently target these new defects. This session will describe the use of the cell-aware test approach to meet this test requirement. Wed 1:45 in the GLOBALFOUNDRIES booth.

SUITE SESSION Intelligent verification has proven to achieve coverage goals 10X faster than constrained random testing, but what if you’ve already written a SystemVerilog testbench? Learn how the latest advances in intelligent testing can now re-use existing constraints and coverage models to achieve coverage 10X faster. Also learn how intelligent testing can generate embedded test programs to verify your SoC at the system level.

SUITE SESSION Bus fabrics can no longer be ignored during SoC verification, as they can cause designs to fall short of functional and performance requirements. Intelligent testing automates bus fabric verification by generating bus traffic that covers all corner case interactions at speed. Learn how Altera used intelligent testing to verify a complex AMBA bus fabric, achieving first silicon success while saving months of time.

SUITE SESSION The design regulations for FPGAs and ASICs in commercial and military aircraft are some of the strictest to adhere to and for good reason – failure of electronics in commercial aircraft can have catastrophic results. While the commercial air industry has mandated the DO-254 hardware design standard, military aerospace companies are adopting design processes similar to DO-254, some even having their own auditors. By taking a design approach that is requirements-driven and well integrated for FPGA and ASIC design creation through device implementation, an excellent design process can be followed that will enable meeting the compliance needs of DO-254 and other such regulations, while also improving the project’s efficiency, productivity, predictability and final chip quality. This session will present advanced chip design methods and practices that are now essential for any mil/aero FPGA or ASIC design project.

SUITE SESSION Explore how the Kronos integrated platform for cell library characterization of standard cell, IO pad and complex cells reduces characterization time enabling complex flip-flops that would normally take 30 minutes to complete on a single machine in as little as one minute. Discuss how Kronos Analyzer can compare library correctness and automatically find cell maps between libraries based on cell behavior.

SUITE SESSION How can you verify twice as much as the last project, in the same amount of time, using the same amount of resource and the same team? This session will focus on what’s new in all areas of the Questa Platform (performance, debug, TB/stimulus creation, coverage closure, low power, SoC verification), and how the platform unifies and automates tools, engines, and methodology into adoptable solutions so that 1+1=3.

SUITE PANEL FinFETs, or so-called 3D transistors, are a key competitive element in all the leading edge IC foundry offerings because FinFETs can achieve much lower power operation than planar transistors. There has been a lot of discussion of the physical and electrical characteristics of FinFETs, but designers are wondering how FinFETs will change the design, verification and test flow. This show floor panel will provide a forum for experts and DAC attendees to learn and interact directly in an informal and entertaining discussion. The panel will be immediately followed by a hosted bar happy hour.

SUITE SESSION Complexities and quality requirements of FPGA and ASIC designs today are demanding new design approaches that start with creation. The level of design abstraction must now be raised above RTL in order to contribute an entire new dimension of benefits to design, especially for multi-core architectures. Raising the design description language up from RTL to electronic system level (ESL), which is TLM-based (transaction level modeling), enables more design to designed, explored, validated, and co-designed with corresponding software and firmware using virtual prototypes to result in faster design cycles, higher quality projects, and higher levels of hardware and software design assurance.

SUITE SESSION Today, FPGA design is not just writing HDL code, but getting the design to meet design goals and validating the complex functionality that has been implemented. There is no substitute for good coding style, but it’s not enough to get the best performance or area utilization results. Expert knowledge of the design tools is invaluable for maximizing results, but who has time to become a tool expert? Once the design goals are met and the FPGA is on the board, does it function as intended? Considerable time is being spent in the "lab" analyzing why a design does not work correctly. In this presentation, new technologies will be showcased in design exploration and validation. Tools should automatically help you get the best results, and rule out or find where possible errors can be introduced in your design between the HDL code and the actual physical implementation on the board. Learn how Mentor Graphics has automated design exploration and design validation processes to maximize your FPGA design effort.

SUITE SESSION Mentor Graphics is bringing revolutionary insight and automation to the most manual portions of custom IC design – the core – routing, placement and floor planning. Hear how our revolutionary interactive custom router is changing the competitive game for its users as it shortens routing time by 10X’s and cuts weeks of our customer’s tape out schedules. Also enjoy a sneak preview of our next deliveries for the automation core.

SUITE SESSION This session will look at proven applications of UVM to move you from the conceptual to the practical. We will explore how UVM provides the ideal infrastructure for adopting new techniques, tools and technologies to improve your verification effectiveness. In addition, we will show how the advanced technologies in Questa use UVM to expand your verification capabilities in ways you may not have even thought of.

PANEL The sheer scale of data generated by EDA tools used on an system-on-chip (SoC) suggest that analytics should play a major role in speedy SoC completion. This is especially true for Functional Verification where analytics can be helpful in sizing the problem, assessing progress, and improving process. However, beyond familiar coverage metrics, this is not the case today. This panel considers statistical analysis, data mining, machine learning, and other analytic methods to gain more insight into verification – and whether the analytics approach can extend to other SoC design areas.