All Mentor@DAC Events
Monday, June 03
Monday, June 03
9:00 AM - 6:00 PM 2 sessions | ||
|---|---|---|
| Booth #912 |
|
Design & Functional Verification |
| Booth #912 |
Products: Mentor Embedded |
Embedded Software |
10:00 AM - 11:00 AM 3 sessions | ||
|---|---|---|
| Suite 4 |
Products: Olympus-SoC |
IC Design & Test |
| Booth #1215 |
Products: Questa, Veloce |
Verification Academy |
| Suite 5 |
Presenter: Hellen Cheng, Senior Manager, IP Development Center, SMIC Products: Calibre PERC |
IC Design & Test |
10:45 AM - 11:00 AM 1 session | ||
|---|---|---|
| Booth 1314 |
Products: Calibre |
IC Design & Test |
11:00 AM - 12:00 PM 4 sessions | ||
|---|---|---|
| Suite 3 |
Products: Veloce |
Design & Functional Verification |
| Suite 4 |
Products: Calibre YieldEnhancer (SmartFill), LFD |
IC Design & Test |
| Suite 5 |
Products: Tessent TestKompress, Tessent LogicBIST, Tessent Diagnosis |
IC Design & Test |
| Booth #1215 |
Products: Questa Low Power |
Verification Academy |
11:00 AM - 1:00 PM 1 session | ||
|---|---|---|
| Tech Conference Rm 15 |
Products: Vista |
Design & Functional Verification |
12:30 PM - 1:30 PM 1 session | ||
|---|---|---|
| Booth 915 |
Products: Calibre |
IC Design & Test |
1:00 PM - 2:00 PM 4 sessions | ||
|---|---|---|
| Suite 3 |
Products: Questa |
Design & Functional Verification |
| Suite 5 |
Products: Calibre xRC and xACT 3D |
IC Design & Test |
| Booth #1215 |
Products: Questa Low Power |
Verification Academy |
| Suite 4 |
Products: Olympus-SoC |
IC Design & Test |
1:30 PM - 1:50 PM 1 session | ||
|---|---|---|
| Booth #912 |
Products: Mentor Embedded |
Embedded Software |
2:00 PM - 3:00 PM 4 sessions | ||
|---|---|---|
| Suite 5 |
Products: Calibre PERC |
IC Design & Test |
| Booth #1215 |
Products: Questa Low Power |
Verification Academy |
| Suite 4 |
Presenter: Yi-Kan Cheng, Deputy Director of the Design Methodology & Kit Development Division, TSMC Products: Calibre |
IC Design & Test |
| Suite 3 |
Products: SystemVision |
Design & Functional Verification |
2:00 PM - 4:00 PM 1 session | ||
|---|---|---|
| Tech Conference Rm 15 |
Products: Vista |
Design & Functional Verification |
3:00 PM - 4:00 PM 4 sessions | ||
|---|---|---|
| Suite 4 |
Products: Kronos |
AMS/Custom IC Design |
| Suite 3 |
Products: Questa |
Design & Functional Verification |
| Booth #2046 |
Moderator: Matthew Hogan, Product Marketing Manager, Calibre Design Solutions, Mentor Graphics Presenter: Ofer Tamir, Director of Design Enablement and Design Support, TowerJazz Presenter: Tim Turner, Reliability Center Business Development Manager, College of Nanoscale Science and Engineering, University at Albany, NY Products: Calibre |
IC Design & Test |
| Booth #1215 |
Products: Questa and UVM |
Verification Academy |
3:15 PM - 4:00 PM 1 session | ||
|---|---|---|
| Booth #509 |
Products: Calibre |
IC Design & Test |
3:30 PM - 3:50 PM 1 session | ||
|---|---|---|
| Booth #912 |
Products: Questa |
Design & Functional Verification |
4:00 PM - 5:00 PM 3 sessions | ||
|---|---|---|
| Suite 4 |
Presenter: Tom Daspit, Product Marketing Manager, Mentor Graphics Products: Pyxis |
AMS/Custom IC Design |
| Suite 3 |
Products: Precision |
Design & Functional Verification |
| Booth #1215 |
Products: Calypto |
Verification Academy |
5:00 PM - 6:00 PM 1 session | ||
|---|---|---|
| Booth #1215 |
Products: Questa Low Power |
Verification Academy |
5:00 PM - 7:00 PM 1 session | ||
|---|---|---|
| Tech Conference Rm 15 |
Products: Vista |
Design & Functional Verification |
Tuesday, June 04
Tuesday, June 04
9:00 AM - 6:00 PM 2 sessions | ||
|---|---|---|
| Booth #912 |
|
Design & Functional Verification |
| Booth #912 |
Products: Mentor Embedded |
Embedded Software |
10:00 AM - 11:00 AM 5 sessions | ||
|---|---|---|
| Suite 3 |
Products: Eldo Premier, Pyxis |
AMS/Custom IC Design |
| Suite 5 |
Products: Tessent MemoryBIST, Tessent IJTAG, Tessent TestKompress |
IC Design & Test |
| Suite 4 |
Products: Calibre YieldEnhancer (SmartFill), LFD |
IC Design & Test |
| Booth #1215 |
Products: Questa, Veloce |
Verification Academy |
| Booth #1314 |
Products: Tessent TestKompress, Diagnose, YieldInsight |
IC Design & Test |
10:30 AM - 11:30 AM 1 session | ||
|---|---|---|
| Booth 915 |
Products: Calibre |
IC Design & Test |
10:30 AM - 12:00 PM 1 session | ||
|---|---|---|
| Tech Conference Rm 16AB |
Products: Calibre |
IC Design & Test |
11:00 AM - 12:00 PM 4 sessions | ||
|---|---|---|
| Suite 4 |
Products: Calibre nmDRC, Multi-patterning |
IC Design & Test |
| Suite 5 |
Products: Olympus-SoC |
IC Design & Test |
| Suite 3 |
Products: Veloce |
Design & Functional Verification |
| Booth #1215 |
Products: Questa |
Verification Academy |
12:30 PM - 1:30 PM 2 sessions | ||
|---|---|---|
| Hall 5 |
Products: Questa |
Design & Functional Verification |
| Hall 5 |
Products: IC Design |
AMS/Custom IC Design |
1:00 PM - 2:00 PM 4 sessions | ||
|---|---|---|
| Suite 5 |
Products: Calibre xRC and xACT 3D |
IC Design & Test |
| Suite 3 |
Products: Questa |
Design & Functional Verification |
| Booth #1215 |
|
Verification Academy |
| Suite 4 |
Products: Olympus-SoC |
IC Design & Test |
2:00 PM - 3:00 PM 4 sessions | ||
|---|---|---|
| Booth #1215 |
Products: Veloce |
Verification Academy |
| Suite 5 |
Presenter: John Ferguson, Director of Marketing, Mentor Graphics Presenter: Michael Hochberg, Director, OpSIS, University of Delaware Products: Calibre nmDRC, LVS, Pyxis, OpSIS Foundry |
IC Design & Test |
| Suite 4 |
Presenter: Ofer Tamir, Director of Design Enablement and Design Support, TowerJazz Products: Calibre PERC |
IC Design & Test |
| Suite 3 |
Products: SystemVision |
Design & Functional Verification |
2:05 PM - 2:20 PM 1 session | ||
|---|---|---|
| Booth 1314 |
Products: Olympus-SoC |
IC Design & Test |
3:00 PM - 4:00 PM 5 sessions | ||
|---|---|---|
| Booth #2046 |
Presenter: Michael Hochberg, Director, OpSIS, University of Delaware Presenter: Robert Patti, CTO and VP of Design Engineering, Tezzaron Presenter: Suk Lee, Senior director, Design Infrastructure, TSMC Products: Calibre |
IC Design & Test |
| Suite 4 |
Products: Kronos |
AMS/Custom IC Design |
| Suite 5 |
Products: ReqTracer, HDL Designer, Visual Elite |
Design & Functional Verification |
| Suite 3 |
Products: Questa |
Design & Functional Verification |
| Booth #1215 |
Products: Questa and UVM |
Verification Academy |
4:00 PM - 5:00 PM 4 sessions | ||
|---|---|---|
| Suite 4 |
Presenter: Tom Daspit, Product Marketing Manager, Mentor Graphics Products: Pyxis |
AMS/Custom IC Design |
| Suite 5 |
Products: Sourcery CodeBench, Vista, Veloce, Questa |
Design & Functional Verification |
| Suite 3 |
Products: Precision |
Design & Functional Verification |
| Booth #1215 |
Products: Questa Formal |
Verification Academy |
Wednesday, June 05
Wednesday, June 05
9:00 AM - 6:00 PM 2 sessions | ||
|---|---|---|
| Booth #912 |
|
Design & Functional Verification |
| Booth #912 |
Products: Mentor Embedded |
Embedded Software |
10:00 AM - 11:00 AM 4 sessions | ||
|---|---|---|
| Suite 5 |
Products: Calibre PERC |
IC Design & Test |
| Suite 3 |
Products: Eldo Premier, Pyxis |
AMS/Custom IC Design |
| Booth #1215 |
Products: Questa, Veloce |
Verification Academy |
| Suite 4 |
Products: Olympus-SoC |
IC Design & Test |
11:00 AM - 12:00 PM 4 sessions | ||
|---|---|---|
| Suite 4 |
Products: Olympus-SoC |
IC Design & Test |
| Suite 5 |
Products: Calibre xRC and xACT 3D |
IC Design & Test |
| Suite 3 |
Products: Veloce |
Design & Functional Verification |
| Booth #1215 |
Products: Questa Formal, Questa CDC |
Verification Academy |
1:00 PM - 2:00 PM 2 sessions | ||
|---|---|---|
| Suite 3 |
Products: Questa |
Design & Functional Verification |
| Booth #1215 |
Products: Questa |
Verification Academy |
1:45 PM - 2:00 PM 1 session | ||
|---|---|---|
| Booth 1314 |
Products: TestKompress |
IC Design & Test |
2:00 PM - 3:00 PM 1 session | ||
|---|---|---|
| Booth #1215 |
Products: Questa InFact |
Verification Academy |
2:30 PM - 3:30 PM 1 session | ||
|---|---|---|
| Booth 915 |
Products: Calibre |
IC Design & Test |
3:00 PM - 4:00 PM 5 sessions | ||
|---|---|---|
| Booth #2046 |
Moderator: Joe Sawicki, Vice President & General Manager, Design-to-Silicon Division, Mentor Graphics Presenter: KK Lin, Director of Design Enablement, Samsung Presenter: Richard Trihy, Director Design Methodology, GLOBALFOUNDRIES Products: Calibre |
IC Design & Test |
| Suite 5 |
Products: ReqTracer, HDL Designer, Visual Elite |
Design & Functional Verification |
| Suite 4 |
Products: Kronos |
AMS/Custom IC Design |
| Suite 3 |
Products: Questa |
Design & Functional Verification |
| Booth #1215 |
Products: Questa InFact |
Verification Academy |
4:00 PM - 5:00 PM 4 sessions | ||
|---|---|---|
| Suite 5 |
Products: Sourcery CodeBench, Vista, Veloce, Questa |
Design & Functional Verification |
| Suite 4 |
Presenter: Tom Daspit, Product Marketing Manager, Mentor Graphics Products: Pyxis |
AMS/Custom IC Design |
| Suite 3 |
Products: Precision |
Design & Functional Verification |
| Booth #1215 |
Products: Questa and UVM |
Verification Academy |
4:00 PM - 5:30 PM 1 session | ||
|---|---|---|
| Tech Conference Rm 16AB |
Products: Questa |
Design & Functional Verification |
Arvind Narayanan is a Product Marketing Manager in the Place and Route division at Mentor Graphics. Prior to Mentor Arvind has held various design, application engineering and marketing positions at Hal Computers, Synopsys and Magma. He has been an active particiapnt in the Unified Power Format initiative. He holds a Masters Degree in Electrical and Computer Engineering (Mississippi State University) and a Masters Degree in Business Administration (Duke University).
Harry Foster is Chief Scientist for Mentor Graphics' Design Verification Technology Division. He holds multiple patents in verification and has co-authored seven books on verification. Harry was the 2006 recipient of the Accellera Technical Excellence Award for his contributions in developing industry standards.
Frank Feng currently works at Mentor Graphics as a Circuit Verification Methodologist for the Calibre product line in the Design to Silicon division. Frank has over twelve years of experience in the EDA industry in the areas of layout and circuit verification and implementation, and four years of experience in semiconductor semi manufacturing. Frank holds a Ph.D. in Physics.
Hellen Cheng is senior manager of the IP Development Center at SMIC, where she is in charge of all in-house IO library development. She has nine years of experience in the semiconductor industry, having joined SMIC in 2003 to focus on library development and ESD design. Hellen also leads a company-wide ESD task force, which plays a key role in SMIC's ESD management strategy. Hellen graduated from Tsinghua University in 2003.
Michael Buehler-Garcia is the Director of Marketing for Calibre Design Solutions in the Design-to-Silicon Division of Mentor Graphics. He manages all aspects of marketing for Calibre design-side product offerings, including product and tactical marketing efforts, strategic positioning, and integration to other business units within Mentor's Design to Silicon organization. Mr. Buehler has experience in all facets of the semiconductor eco-system, including EDA companies, foundries, fabless companies, and their end customers. He has over 25 years of experience, including executive positions at companies such as iRoC Technologies and PDF Solutions, as well as Chartered Semiconductor, one of the largest foundries in the world, and Cadence Design Systems, one of the world's largest EDA companies. He brings a unique perspective for optimizing and leveraging supply chains, along with expertise of how both multinational and start-up companies can succeed in the new world of outsourcing all elements of a company. Coupled with this hands-on knowledge is the capability to create and drive overall company strategic direction from endgame strategies to the underlying product roadmap and definition.
Jim Kenney has over 25 years of experience in hardware emulation and logic simulation and has spent the bulk of his career at Mentor Graphics Corporation. Jim has held responsibility for analog, digital and mixed-signal simulation, hardware/software co-verification and hardware emulation. He is currently the Marketing Director for Mentor's Emulation Division. Jim holds a BSEE from Clemson University.
Jean-Marie Brunet is the Director Product Marketing for Model Based DFM and Place-and-Route Integration at Mentor Graphics Corporation. Over the past 18 years, he has served in application engineering, marketing and management roles in the EDA industry, and has held IC design and design management positions at STMicrolectronics, Cadence, and Micron among others. His experience includes working with pure-play foundries to resolve complex yield issues related to OPC and RET. He holds a Master's degree in Electrical Engineering from I.S.E.N Electronic Engineering School in Lille, France.
Stephen Pateras is product marketing director for Mentor Graphics Silicon Test products. His previous position was VP Marketing at LogicVision. While at LogicVision Stephen also held senior management positions in engineering, and was instrumental in defining and bringing to market several generations of LogicVision’s semiconductor test products. From 1991 to 1995, Stephen held various engineering lead and management positions within IBM’s mainframe test group. He received his Ph.D. in Electrical Engineering from McGill University in Montreal, Canada
Jon McDonald is Sr. Technical Marketing Engineer at Mentor Graphics. He received a BS in Electrical and Computer Engineering from Carnegie Mellon and an MS in Computer Science from Polytechnic University. He has been active in digital design, language based design and architectural modeling for over 15 years. Prior to joining Mentor Graphics Mr. McDonald held senior technical engineering positions with Summit Design, Viewlogic Systems and HHB Systems.
Roger Sabbagh has over 19 years of experience in system and silicon design & verification, CAD methodology development and technical marketing. As a verification technologist at Mentor Graphics, Mr. Sabbagh is focused on the areas of assertion based verification, formal functional verification and clock-domain crossing verification. In this position, he works with leading edge silicon design teams to help them adopt advanced methodologies. Prior to joining Mentor, Mr. Sabbagh has held positions in CAD methodology and design at Nortel Networks and Worldheart. Mr. Sabbagh holds a bachelor degree in electrical engineering from Carleton University in Ottawa, Canada.
Carey Robertson is a Director of Product Marketing at Mentor Graphics Corp., overseeing the marketing activities for Calibre PERC, LVS and extraction products. He has been with Mentor Graphics for 14 years in various product and technical marketing roles. Prior to Mentor Graphics, Carey was a design engineer at Digital Equipment Corp., working on microprocessor design. Carey holds a BS from Stanford University and an MS from UC Berkeley.
Randy Grover has 29 years of experience in ASIC and SoC design, EDA development and technical sales support with STMicroelectronics, Texas Instruments, Cooper & Chyan Technology, and Cadence Design Systems. He has worked with a large variety of customer design organizations worldwide in both design engineering and management roles. Douglas holds BSEE (Computer Hardware Design) from Auburn University.
Matthew Hogan is a Product Marketing Manager for Calibre Design Solutions at Mentor Graphics, with over 15 years of design and field experience. He is an IEEE Senior member and ACM member and holds a Bachelor of Engineering from the Royal Melbourne Institute of Technology and an MBA from Marylhurst University. He is actively working with customers who have an interest in Calibre PERC.
Ms. Burns has over 25 years of experience in the chip design and the EDA industries in various roles of engineering, applications engineering, technical marketing and product management. She is currently the Product Manager in the Design and Verification Technology Division at Mentor Graphics responsible for simulation with Questa and ModelSim. Prior to Mentor Graphics, Ms. Burns has held engineering and marketing positions at CoWare, Cadence, Synopsys, Viewlogic, Computervision and Intel. She holds a BSCpE from Oregon State University.
John Ferguson is the Lead Technical Marketing Engineer for the Calibre product line at Mentor Graphics in Wilsonville, Oregon. He received a BS degree in Physics from McGill University in 1991, an MS in Applied Physics from the University of Massachusetts in 1993, and a PhD in Electrical Engineering from the Oregon Graduate Institute of Science and Technology in 2000. He has worked extensively in the area of physical design verification.
Dr. Subba Somanchi currently serves as Director of the System Modeling & Analysis business unit in the System-Level Engineering Division at Mentor Graphics. As such, he is responsible for the SystemVision and BridgePoint product lines. Somanchi has worked on SystemVision for the past 13 years, serving as Product Architect and Engineering Manager after holding the position of Staff Engineer. He also worked as a Model Development Engineer at Analogy, Inc., working on schematic-driven mechatronic simulation products. Somanchi holds a Ph.D. in Electrical Engineering from Washington State University and an MBA from Marylhurst University.
Ahmed Eisawy is a member of the Technical & Product Marketing team ofthe Analog/Mixed-Signal group - part of the Deep Sub-micron Division - at Mentor Graphics. He's the product marketing manager for Kronos, the Cell Library Characterization and Validation, as well as Artist Link, the integration of the Mentor A/MS simulators into Cadence Virtuoso Analog Design Environment. For the last six years, he's been working as a member of the marketing team to drive the development of Analog/Mixed-Signal simulators forward with new technologies as well as engage with customers for evaluations, training & education, solving complex problems as well as help the customers through methodology assessments to improve their flow. Previously, Ahmed worked for six years in technical support where he worked closely with customers, helping resolve problems and help formulate the customer needs into tool enhancements. He received his BSEE from Cairo University in 1999 and his MSEE from the same university in 2002.
Ofer Tamir is the Director of design enablement and design support at TowerJazz. He has a Master’s Degree in computer science and has worked for 25 years as an EDA engineer at companies such as National Semiconductor (CAD engineer & CAD/ layout verification) and DSPG (CAD manager).
Tom Fitzpatrick is currently a Verification Technologist at Mentor Graphics Corp. where he brings over two decades of design and verification experience to bear on developing advanced verification methodologies, particularly using SystemVerilog, and educating users on how to adopt them. He has been actively involved in the standardization of SystemVerilog, starting with his days as a member of the Superlog language design team at Co-Design Automation through its standardization via Accellera and then the IEEE, where he has served as chair of the 1364 Verilog Working Group, as well as a Technical Champion on the SystemVerilog P1800 Working Group. At Mentor Graphics, Tom was one of the original designers of the Advanced Verification Methodology (AVM), and later the Open Verification Methodology (OVM), and is the editor of Verification Horizons, a quarterly newsletter with approximately 40,000 subscribers. He is a charter member and key contributor to the Accellera Verification IP Technical Subcommittee. He has published multiple articles and technical papers about SystemVerilog, verification methodologies, assertion-based verification, functional coverage, formal verification and other functional verification topics.
Juan C. Rey is the Senior Engineering Director for the Calibre product line in the Design to Silicon Division at Mentor Graphics Corporation. His group is responsible for the architecture, design and development of Mentor’s software product line for integrated circuit physical verification and tape out tasks such as design rule checking, layout vs. schematic verification, capacitance, resistance and inductance extraction, resolution enhancement, mask data preparation and design for manufacturing. Juan has 30 years of software development experience ranging from research activities at Stanford University (EE department), to development and management of electronic design automation and process and device modeling software at Technology Modeling Associates, Cadence and Mentor Graphics. Juan also represents his company at the Executive Technology Advisory Board of Semiconductor Research Corporation (SRC) and is responsible for the IP portfolio and research initiatives of his division.
If there is something Mentor is not doing in the area of functional verification, but you think we should be, Steve wants to know about it. Steve is bringing his extensive experience spanning development of HDL simulators, applications engineering, consulting, and technical and product marketing to direct Mentor into new market opportunities for verification and coordinate between Mentor's verification-related divisions.
Roger Do is Synthesis Product Specialist at Mentor Graphics. He has over 16 years of FPGA experience, including previous roles in corporate and field applications and product marketing with Texas Instruments, Lucent Technologies, and Lattice Semiconductor. Roger holds a B.S. in Electrical Engineering from Texas A&M University.
Abhishek Ranjan is Senior Director of Engineering at Calypto Design Systems where he is responsible for development of the RTL power optimization product, PowerPro. Prior to Calypto, he held various leadership and management positions at Xilinx Inc., Hierarchical Design, and Monterey Design Systems. Abhishek received a Bachelor of Technology in Electrical Engineering from the Indian Institute of Technology, Kanpur, India. He holds a Master’s degree in Computer Engineering from Northwestern University, Illinois, USA. Abhishek holds several patents in the field of VLSI CAD and has published dozens of research papers in reputable conferences and journals.
Linda Fosler is a seasoned professional providing marketing and operations management expertise for a diverse group of technologies and industries including computer systems, semiconductors, embedded systems and software and hardware design and verification tools. Linda is currently the director of marketing for the deep submicron (DSM) division of Mentor Graphics. Prior to this Linda was Vice President of Marketing and Business Development for VaST Systems, Esterel Technologies and IKOS Systems, as well as Vice President of Software Quality at Cadence Design Systems. Past accomplishments also include working as an independent consultant for a host of electronics related clients.
Valeriy Sukharev is the Technical Lead and Principle Engineer of the Design-to-Silicon division of Mentor Graphics Corporation. Dr. Sukharev leads research and development of new full-chip modeling and simulation capabilities for the semiconductor processing and DFM/DFR applications. He has authored and edited a number of books, published more than 100 papers in scientific journals and holds 20 plus U.S. patents. He has been with Mentor Graphics R&D for five years. Prior to Mentor Graphics, Dr. Sukharev was a Visiting Professor with Brown University, Providence, RI, and a Guest Researcher with the National Institute of Standards and Technology (NIST), Gaithersburg, MD. He held senior technical positions at LSI Logic Advanced Development Lab, Milpitas, CA. He holds Ph.D. in physical chemistry from the Karpov Institute of Physical Chemistry, Moscow, Russia.
Michael White is the Director of Product Marketing for Mentor Graphics' Calibre Physical Verification products. Prior to Mentor Graphics, he held various product marketing, strategic marketing and program management roles for Applied Materials, Etec Systems and the Lockheed Skunk Works. Michael received an MS in engineering management from the University of Southern California MBA School, and a BS in System Engineering from Harvey Mudd College.
Mark Olen is currently a Functional Verification Technologist at Mentor Graphics Corp. He has spent over thirty years in semiconductor design verification and manufacturing test, and has authored papers in the areas of intelligent testbench automation, design for test technology, and semiconductor manufacturing test automation. He wrote his first testbench in 1981 at Raytheon, and went on to spend ten years working at Teradyne in the ATE and DFT industries. He became Vice President of Cascade Microtech's thin film wafer probe division, before co-founding Lighthouse Design Automation where graph-based Intelligent Testbench Automation was first successfully applied to semiconductor design verification. Mark graduated from MIT with a BS in EE&CS.
Amr M. Tosson graduated with honors from the department of Electronics and Communications Engineering of Cairo University in 2006. He obtained his MSc in Electronics from the same department in 2009. In addition to pursuing a PhD degree from the University of Waterloo, Amr is a Sr. Software Development Engineer at Mentor Graphics
Joseph Adesanya works at Ostendo Technologies as the ASIC System’s Manager and his core duties encompassed all phases of product development; from specification and architectural design, down to FPGA prototyping and ASIC hardening. Before joining Ostendo, Joseph worked at General Atomics as a principal staff engineer where he worked on Ultra Wide Band (UWB) based solutions ranging from unattended ground sensor networks to USB and streaming media applications. Prior to General Atomics, Joseph has held ASIC lead positions at Hughes Network Systems and Nokia Telecommunications (Finland). Joseph holds a MSC degree in Mobile, Personal and Satellite Communications and a BENG degree in Electrical and Electronics Engineering from the University of Westminster (UK). He is a senior member of Institute of Electrical and Electronics Engineers (IEEE) and a member of the Institution of Engineering and Technology (IET).
Michael Hochberg is a co-founder of Luxtera, a photonics component firm, and also directs OpSIS, a foundry service for silicon photonics in which the community shares the cost of fabricating complex chip-scale systems across many projects. A longtime photonics reasearcher, Hochberg's work has been featured in Nature Materials, Nature, and other journals.
Valerie Rachko is the director of HDL & ESL design creation marketing in the Design Creation business unit of ESD, located in Wilsonville. Valerie has been marketing HDL design products for Mentor Graphics since 1990, ranging from creation, analysis, reuse, checking, verification, synthesis, and design management, with more recent expansion into UVM/OVM and ESL. She holds Bachelor of Science and Master of Science degrees in electrical engineering from Fairleigh Dickinson University, USA, graduating in both with summa cum laude honors. She is also a magma cum laude Master of Business Administration in marketing graduate from Seton Hall University, USA. Prior to joining Mentor Graphics, she was an ASIC designer for over five years.
Vigyan Singhal is the CEO of Oski Technology, a services company focussed on formal verification. Vigyan has practised formal verification since 1993. Previously he founded two startups, Jasper Design Automation and Elastix. He has a PhD from UC Berkeley, and BTech from IIT Kanpur.
Ram Narayan is a Consulting Member of Technical Staff in Oracle Labs. He is a member of the RAPID Hardware Verification Team since January 2013. Prior to joining Oracle, Ram was a Principal Member of Technical Staff in the Platform Emulation Team at Advanced Micro Devices. In this capacity, he was driving improvements to the pre-silicon emulation strategy to impact the post-silicon validation effort and reduce the time to market. Ram joined AMD from Mentor Graphics in 2010. As an Application Engineer at Mentor Graphics, he helped Mentor's customers realize their verification goals with a range of technologies including Simulation, Formal Verification, Assertion and Coverage Based Verification, Testbench Automation, Hardware Software Co-verification and Hardware Emulation. Prior to joining Mentor Graphics, Ram was a Design Engineer in the K5 and K7 microprocessor design teams at AMD from 1993. His responsibilities included Architecure, RTL Design, Verification, Microcode Development and Hardware Emulation. Ram has 26 patents granted in the US. Ram received a B.Tech. in Electrical Engineering at The Indian Institute of Technology, Bombay in 1991 and an M.S. in Computer Engineering at The University of Texas at Austin in 1994.
Dennis B. Brophy is Director of Strategic Business Development at Mentor Graphic Corporation. He is also volunteer vice-chair and past chair of Accellera, an electronic design automation standardization group. Dennis has been in the electronic design automation industry for the past 33 years. He was first with Hewlett-Packard for five years, and then joined Mentor Graphics, where he has held several positions over the past 28 years. He is a member of the IEEE Standards Association (SA) Board of Governors (BoG) and Chair of the IEEE SA Corporate Advisory Group (CAG). He is secretary of the IEEE 1800 SystemVerilog Working Group and IEEE 1666 SystemC Working Group. Dennis is also a member of the American National Standards Institute (ANSI) and is a member of the United States National Committee for EDA standards. He is a co-convenor of IEC TC91 WG13. Dennis received a Bachelor of Science degree from the University of California at Davis in electrical engineering and computer engineering in 1980.
Sawicki is the vice president and general manager of the Design-to-Silicon division. A leading expert in IC nanometer design and manufacturing challenges, Sawicki is responsible for Mentor's industry-leading design-to-silicon products, including the Calibre physical verification and DFM platform and Mentor's Tessent design-for-test product line. Sawicki joined Mentor Graphics in 1990 and has held previous positions in applications engineering, sales, marketing and management. He holds a BSEE from the University of Rochester, an MBA from Northeastern University's High Technology Program, and has completed the Harvard Business School Advanced Management Program.