Maximizing Productivity in Advanced SoC and Custom Design Flows with Calibre Integrations
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Calibre is the industry touchstone for physical and electrical verification and should be used at each stage of the design process, integrated with your design tools. Sign-off level verification at 28 and 20nm isn’t something that should be done only at the end of the long physical design process. The complexities of these technologies and the aggressive architectures of leading-edge designs mean that sign-off verification is part of every step in the process – IP design, abstract generation, synthesis, power-ground generation, clock-tree synthesis, P&R, and integration.
Take this approach and what do you get? A no compromises needed solution. Integrating Calibre, the fastest, most reliable verification solution, at every step of the design flow enables you to march confidently from concept to tape-out.
What You Will Learn
- How to streamline the designer’s work
- Best practices to maximize engineer productivity at advanced process nodes
- How to easily integrate Calibre into your design flow to maximize manufacturability
About the Presenter
Director of Product Marketing
Calibre User Interface and Integration
Joe Davis' career in the IC industry spans over 20 years at high-profile companies such as Analog Devices, Texas Instruments and PDF Solutions. At Mentor, he leverages his previous experience designing ICs and developing tools for IC designers/manufacturers to improve data visualization and engineering workflow. Prior to joining Mentor, Joe was the senior product manager for yield simulation products at PDF Solutions where he managed semiconductor process-design technologies and services, including yield simulation and analysis tools. Joe earned his BSEE, MSEE and Ph.D. in Electrical and Computer Engineering from North Carolina State University.
Who Should Attend
- Digital implementation designers
- Custom layout designers
- CAD engineers
- Engineering and CAD management