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Partner Activities

Mentor offers the broadest support for the electronics ecosystem/supply chain. That’s why you’ll find Mentor experts sharing in a numerous partner activities on the exhibition floor—both in our booth and at our partners’ locations.

Suite B
  • Better Layout in Less Time: AMD’s Experience with Calibre RealTime at 20nm and Below
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    TECHNICAL SESSION Physical implementation is significantly more challenging at 20nm than at previous nodes. Introducing Calibre RealTime into the production flow at AMD enabled designers to meet this challenge and improve the quality of the layout at the same time. Calibre RealTime provides immediate feedback for implementation and the ability to optimize the layout with full sign-off feedback. This enables us to make last-minute edits with sign-off confidence, and to reduce the number of batch DRC iterations required to reach tape-out.

Presenter: Kalyan Chakravarthy, Member of Technical Staff, AMD
Presenter: Srinivas Velivala, Calibre TME, Mentor Graphics
Room 105
  • Power Aware Clock Domain Crossing Verification
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    TECHNICAL SESSION Formal and static methods, which analyze a design directly rather than depending on large numbers of simulation vectors, are becoming increasingly important in the world of modern design. In the first part of this session, real-world practitioners who have been successful with formal verification describe case studies and use them to supply useful advice for those who wish to achieve similar results. Then we move on to describe some new and powerful uses for static and formal techniques in conjunction with other tools and methods, providing new insights into IP integration, clock domain crossings, power issues, and clock/reset design.

Presenter: Roger Sabbagh, Product Marketing Manager, Mentor Graphics
Presenter: Saumitra Goel, Lead Consultant Staff, Mentor Graphics
Booth 2007
  • Block-to-System Verification of ARM-Based SoCs
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    TECHNICAL SESSION SoCs incorporate ARM processor and fabric IP to meet requirements in functionality and time-to-market. Employing excellent functional verification solutions from block design to system verification ensure SoCs deliver required functionality and within schedule. Mentor Graphics will discuss functional verification solutions spanning from block-level verification to full system verification.

Presenter: Steve Bailey, Director of Emerging Technologies, Mentor Graphics
Booth 2007
  • Vista Virtual Prototyping for HW/SW Debug and Analysis
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    TECHNICAL SESSION Traditional embedded system design is transforming to a new world of Virtual embedded software and hardware design. Mentor’s virtual prototyping solution is revolutionizing embedded platform-based design by enabling debug of hardware/software complex interactions and by providing analysis capabilities not achievable with traditional simulation or on prototyping boards. It offers a tightly coupled HW/SW debug, analysis and verification capabilities that are changing the traditional design paradigm on prototyping boards. This includes observing the behaviour of the platform’s software in a non-intrusive manner, without introducing any observation effects.
    This session will illustrate the level of control, visibility and analysis capabilities available on a reference virtual prototype to guide efficient software and hardware development that meets the functionality and performance goals.

Presenter: Shabtay Matalon, Market Development Manager, Mentor Graphics
Booth 1113
  • AMBA®CHI and the Mentor Enterprise Verification Platform
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    TECHNICAL SESSION The complexity and size of fabrics based on AMBA® 5 CHI present new verification challenges. This presentation from ARM and Mentor Graphics gives a brief introduction to the CHI protocol and then describes how a verification flow based on Mentor’s CHI VIP, emulation operating system, hardware debugger and software debugger can be used to verify caches and fabrics that use this AMBA 5 protocol.

Presenter: William Orme, Strategic Marketing Manager, Systems & Software Group, ARM
Booth 1113
  • You Think You Have Good Stimulus: System-Level Distributed Metrics Analysis and Results
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    TECHNICAL SESSION Developing and maintaining an effective and efficient verification suite for a complex system requires the ability to measure, understand, and improve the environment. Distributed, hierarchical caches are an example of interacting components within an SoC. Understanding how well the components are verified is a challenge since the cache interactions are complex, the components are distributed across an environment, and the data is spread across one or more regressions. This session discusses the challenges of collecting metrics, providing the visualization to understand complex state machine interactions, and then reviews results of a regression analysis.

Presenter: Alan Hunter, ARM
Booth 1113
  • Formal Apps In-Depth: Connectivity and Register Verification
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    TECHNICAL SESSION Formal apps improve design quality and shorten the schedule for dealing with specific bottlenecks that occur during the verification process. In this session, we will discuss two of the most widely used apps in detail: connectivity verification and control and status register (CSR) verification. Come find out all you ever wanted to know about these apps, from someone who’s “been there, done that”!

Presenter: Mark Eslinger, Mentor Graphics
Suite B
  • Samsung Ecosystem Collaboration with Mentor for DFM at 14nm and Below
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    TECHNICAL SESSION For the 14nm node, Mentor and Samsung have collaborated extensively to create a comprehensive DFM solution that includes proven solutions for litho simulation, pattern matching, critical area analysis (CAA) and advanced filling. Come to this session to understand what was done and how it can help you move to 14nm.

Presenter: Jean-Marie Brunet, Product Marketing Director for Design for Manufacturing (DFM) and Place & Route Integration, Mentor Graphics
Presenter: Kuang-Kuo Lin, Director of Foundry Design Enablement at America Headquarters Device Solutions, Samsung Semiconductor
Booth 819
  • Mentor Graphics Formal Verification Meets the Need for Complex Designs
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    TECHNICAL SESSION The latest research on formal verification has resulted in new and more powerful algorithms to solve the challenges of verifying very complex designs that are not well addressed by traditional methods. Tools like Mentor’s Questa Formal have also evolved to make it easy to apply formal verification to specific use cases. In this session we’ll show Samsung case studies that demonstrate how formal verification tools improve project schedules and design quality.

Presenter: Roger Sabbagh, Product Marketing Manager, Mentor Graphics
Booth 819
  • Ensuring Manufacturability at Advanced FinFET Process Nodes
Presenter: Michael Buehler-Garcia, Senior Director of Marketing for Calibre Design Solutions, Mentor Graphics
Booth 1107
  • Calibre Signoff DRC in OpenAccess-enabled Design Environments
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    TECHNICAL SESSION Calibre RealTime provides signoff DRC, multi-patterning, and pattern matching capabilities in OpenAccess-enabled design environments, saving engineers time and improves the quality of the layout by providing instant feedback as layout is created or edited. This capability is made possible by the OA runtime model, which provides an open API to access data inside the design tool as edits are made.

Presenter: Srinivas Velivala, Calibre TME, Mentor Graphics
Booth 413
  • ESD Challenges at Advanced Nodes with Complex Design
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    TECHNICAL SESSION Reliability issues usually require design verification driven from circuit schematics to the corresponding layout data. Traditional DRC engines are unable to distinguish specific design functions of layout geometries. Manual markers are usually required to enable automated checks. However, erroneous markers can jeopardize reliability verification. Calibre PERC provides a fully automated and comprehensive reliability verification platform to validate design intent. It has been successfully used to identify issues in such diverse areas as ESD, latch-up, EOS, ERC and other design issues in both early design schematics and stream out layout databases. Calibre PERC is the first, and currently the only available tool with a qualified design kit from several major foundries for reliability sign-off. In this session, Mentor Graphics and Semiconductor Manufacturing International Corporation (SMIC) discuss reliability verification with Calibre PERC.

Presenter: Matt Hogan, Product Marketing Manager, Calibre Design Solutions, Mentor Graphics
Presenter: Valerie Rachko, Marketing Director, Mentor Graphics
Booth 413
  • Successful Application of Calibre LFD at SMIC
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    TECHNICAL SESSION Design for Manufacturing(DFM) is becoming indispensable for integrated circuits (ICs) design as the manufacturing difficulty and design complexity both are increasing exponentially diving into the advanced nodes. Calibre LFD (Litho Friendly Design) is sign-off litho checking tool that helps identify litho hotspots and verify designs have sufficient litho process window. SMIC has developed and certified the Calibre LFD kits and flow in litho DFM section to support designers to achieve litho-friendly designs starting from 65nm to 28nm nodes. The kits could be used easily by designers from cell to block and chip level in the whole design cycle, of course, the earlier you use, the more chance that you may get an optimized and robust design. Meanwhile, SMIC also offers the LFD checking service to designers anytime ahead of design tape-out and provides verified hotspot fixing guidelines.

Presenter: Joe Kwan, Foundries Program Manager, Mentor Graphics
Presenter: Tom Daspit, Product Marketing Manager, Mentor Graphics
Suite B
  • 2-5X Design Productivity Improvement in 14FDSOI layout designs: ST’s experiences with Calibre RealTime
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    TECHNICAL SESSION At 20nm and below the significant increase in the number and complexity of DRC rules makes DRC verification challenging. This leads to increase in total DRC cycle-time that in turn leads to longer design time. Using Calibre RealTime in the 14FDSOI design flow at ST enabled us to improve our design productivity by a factor of 2-5X while maintaining the quality of the layout design. Calibre RealTime made sign-off DRC a part of our standard design flow by providing immediate signoff-quality DRC feedback within the design environment.

Presenter: Srinivas Velivala, Calibre TME, Mentor Graphics
Suite C
  • Customer Success using Olympus-SoC P&R: ST Microelectronics
Booth 1801
  • Helping Ensuring Your FinFET Designs Ramp to Production As Fast as Possible with Calibre and Tessent
Presenter: Michael Buehler-Garcia, Senior Director of Marketing for Calibre Design Solutions, Mentor Graphics
Presenter: Steve Pateras, Product Marketing Director, Silicon Test Products, Mentor Graphics
Booth 1801
  • Designing “Cool” ASIC and SoC Designs with PPA Optimized  Memory IPs in the TSMC Environment
Presenter: Farzad Zarrinfar, Director, Mentor Graphics
Booth 1801
  • Mentor RTL to GDS Digital Implementation for best PPA at Advanced Nodes 
Presenter: Arvind Narayanan, Product Marketing Manager, Integrated Circuit Implementation Division, Mentor Graphics
Booth 1801
  • Partnering to Advance Nanometer-Scale Circuit Verification – Mentor Graphics Analog FastSPICE Platform and TSMC
Presenter: Mick Tegethoff, Product Marketing Manager, Mentor Graphics