PARTNER KIOSK PRESENTATION Successful IC manufacturing at 20nm requires some important design optimization strategies. Fill becomes much more sophisticated because it’s no longer just about planarity, but a whole range of interrelated effects, such as etch, lithography, stress, and rapid thermal annealing (RTA). Verification of latch-up immunity depends on automated measurements and analysis, for example, determining the resistance of paths in output driver arrays as a function of device spacing. Other circuit checks address reliability issues, including electrostatic discharge (ESD), electrical overstress (EOS), and errors arising from signals crossing multiple power domains. This session will highlight areas where Mentor and GLOBALFOUNDRIES have collaborated to deliver solutions to new design enabling challenges.