Mentor@DAC 2013: Partner Activities

SUITE SESSION This session will present some of the verification practices needed for efficient validation and verification of ARM v8 family compute sub-systems. We will explore some practical approaches to verification challenges for reuse, scalability and integrating cache coherency systems and solutions.

PARTNER KIOSK PRESENTATION The ability to effectively identify yield limiting design feature is a key asset for foundries and fabless semiconductor companies. This presentation covers the result of a collaboration between Mentor Graphics and GLOBALFOUNDRIES to rapidly identify systematic defects and critical design features based on silicon data [1-4]. Layout-aware diagnosis identifies the location and classification of defects causing manufacturing test failures. Specialized statistical analysis coupled with design profiling data (such as critical feature analysis) then determines the root cause of yield loss and separates design and process induced defects.

PARTNER KIOSK PRESENTATION Successful IC manufacturing at 20nm requires some important design optimization strategies. Fill becomes much more sophisticated because it’s no longer just about planarity, but a whole range of interrelated effects, such as etch, lithography, stress, and rapid thermal annealing (RTA). Verification of latch-up immunity depends on automated measurements and analysis, for example, determining the resistance of paths in output driver arrays as a function of device spacing. Other circuit checks address reliability issues, including electrostatic discharge (ESD), electrical overstress (EOS), and errors arising from signals crossing multiple power domains. This session will highlight areas where Mentor and GLOBALFOUNDRIES have collaborated to deliver solutions to new design enabling challenges.

PARTNER KIOSK PRESENTATION One of the predominant P&R challenges is realizing best power, performance and area (PPA), a goal that is more difficult to achieve at advanced nodes due to complex DRC / DFM rules, double patterning, growing design sizes, low power requirements and increasing process and design variations. It is also critical to reduce the die size to justify the cost of moving to smaller nodes. This session shows advanced technologies for efficient design closure such as concurrent PPA optimization, pseudo flat flow methodology and DRC/DP signoff during implementation.

PARTNER KIOSK PRESENTATION 3D transistors, or FinFETs, exacerbate concerns about quality and reliability at 16nm and below. While there has already been a lot of research into the types of defects expected with FinFETs, characterizing these defect mechanisms is only the first step. We also need a methodology for generating test patterns that efficiently target these new defects. This session will describe the use of the cell-aware test approach to meet this test requirement.

SUITE SESSION TowerJazz, the global specialty foundry leader, is now providing Calibre PERC rule decks that enable their customers to perform circuit reliability verification during signoff. TowerJazz provides highly customized electrostatic discharge (ESD) and power management circuit checks based on their specific manufacturing processes. Many of these checks have been automated for the first time by taking advantage of the Calibre PERC product’s unique ability to combine schematic (net list) and physical layout information, which goes beyond the scope of traditional LVS, DRC and ERC tools. This is a one-time, limited seating session for advanced Calibre users. Register today to reserve your spot.

SUITE SESSION When leading edge customers first transitioned to 20nm they encountered issues not experienced in prior nodes with the set-up of hardware, flows, and use models during chip verification. TSMC and Mentor worked with these customers to resolve the issues resulting in successful tape-outs of these customers’ designs. TSMC and Mentor will present best practices learned from that experience to help other customers smoothly tape-out their advanced process node designs.