Mentor@DAC 2013: Partner Activities

Mentor offers the broadest support for the electronics ecosystem/supply chain. That’s why you’ll find Mentor experts sharing in a numerous partner activities on the exhibition floor—both in our booth and at our partners’ locations.

Booth 912
  • ARM Connected Community & Functional Verification
Booth 912
  • ARM Connected Community & Mentor Embedded
Presenter: Jamie Little, Alliance Marketing Manager, Embedded Software, Mentor Graphics
Booth 912
  • Enabling ARM-based Silicon with 100 Million lines of Embedded Software
Presenter: Jamie Little, Alliance Marketing Manager, Embedded Software, Mentor Graphics
Booth 912
  • Functional Verification of ARM-based subsystems and SoCs with Questa
Presenter: Steve Bailey, Director of Emerging Technologies, Mentor Graphics
Room 15
  • Supercharge Your GPU Abstract

    WORKSHOP In this tutorial, we will present the evolution of an OpenGL ES application development and execution flow across software and hardware threads and through virtual and physical embedded hardware targets. The entire flow is driven with a unified native Software IDE with embedded hardware visibility and profiling features.

    The tutorial will delve into all aspects of software-driven debugging and optimization while migrating from a pure virtual prototype target, and software rendering implementation across to graphical processing engine executing on an emulator or a physical board.

    The real-world impact of the flow described in this tutorial is far reaching. Graphical applications such as visual computing, image processing and 3D animation and navigation are a fundamental component of many modern mobile, automotive and gaming devices.

Presenter: Jon McDonald, Sr. Technical Marketing Engineer, Mentor Graphics
Booth 1215
  • Coherent Verification of ARM-based SoCs Abstract

    SUITE SESSION This session will present some of the verification practices needed for efficient validation and verification of ARM v8 family compute sub-systems. We will explore some practical approaches to verification challenges for reuse, scalability and integrating cache coherency systems and solutions. Tues. 13:00, Verifcation Academy booth.

Booth 1314
  • Achieving Best PPA at Advanced Nodes using Olympus-SoC Abstract

    PARTNER KIOSK PRESENTATION One of the predominant P&R challenges is realizing best power, performance and area (PPA), a goal that is more difficult to achieve at advanced nodes due to complex DRC / DFM rules, double patterning, growing design sizes, low power requirements and increasing process and design variations. It is also critical to reduce the die size to justify the cost of moving to smaller nodes. This session shows advanced technologies for efficient design closure such as concurrent PPA optimization, pseudo flat flow methodology and DRC/DP signoff during implementation. Tue 2:05 in the GLOBALFOUNDRIES booth.

Presenter: Prashant Varshney, Product Engineering Director, Mentor Graphics
Booth 1314
  • Ensuring FinFET defect Coverage with Cell-Aware Test Abstract

    PARTNER KIOSK PRESENTATION 3D transistors, or FinFETs, exacerbate concerns about quality and reliability at 16nm and below. While there has already been a lot of research into the types of defects expected with FinFETs, characterizing these defect mechanisms is only the first step. We also need a methodology for generating test patterns that efficiently target these new defects. This session will describe the use of the cell-aware test approach to meet this test requirement. Wed 2:30 in the TSMC booth.

Presenter: Stephen Pateras, Product Marketing Director, Mentor Graphics
Booth 1314
  • Identifying Critical Design Features from Silicon Results Abstract

    PARTNER KIOSK PRESENTATION The ability to effectively identify yield limiting design feature is a key asset for foundries and fabless semiconductor companies. This presentation covers the result of a collaboration between Mentor Graphics and GLOBALFOUNDRIES to rapidly identify systematic defects and critical design features based on silicon data [1-4]. Layout-aware diagnosis identifies the location and classification of defects causing manufacturing test failures. Specialized statistical analysis coupled with design profiling data (such as critical feature analysis) then determines the root cause of yield loss and separates design and process induced defects. Tue 10:00 in the GLOBALFOUNDRIES booth.

Presenter: Ken Amstutz, Sr. Application Engineer, Mentor Graphics
Booth 1314
  • Optimizing your Verification Flow for Advanced Designs Abstract

    PARTNER KIOSK PRESENTATION Successful IC manufacturing at 20nm requires some important design optimization strategies. Fill becomes much more sophisticated because it’s no longer just about planarity, but a whole range of interrelated effects, such as etch, lithography, stress, and rapid thermal annealing (RTA). Verification of latch-up immunity depends on automated measurements and analysis, for example, determining the resistance of paths in output driver arrays as a function of device spacing. Other circuit checks address reliability issues, including electrostatic discharge (ESD), electrical overstress (EOS), and errors arising from signals crossing multiple power domains. This session will highlight areas where Mentor and GLOBALFOUNDRIES have collaborated to deliver solutions to new design enabling challenges. Mon 10:45 in the GLOBALFOUNDRIES booth.

Presenter: Michael Buehler-Gracia, Director of Marketing for Calibre Design Solutions, Mentor Graphics
Suite 5
  • Preparing for Pervasive Photonics Abstract

    SUITE SESSION Silicon photonics is using silicon for the fabrication of light-based devices—such as lasers, amplifiers, converters, filters and splitters. Current applications include ultra-fast chip-to-chip optical interconnects, optical routers and signal processors. Visionaries see SP as an enabling technology that will impact many facets of life through entertainment, medical discovery, communications, information storage, and manufacturing. This session discusses the impact photonics will have on today’s IC design and manufacturing processes, the tool requirements for SP, foundry options, new applications that will SP open up, and new challenges it will present to IC designers. Tue 2:00, Mentor booth.

Presenter: Angela Wong, Technical Marketing Engineer, Mentor Graphics
Presenter: John Ferguson, Director of Marketing, Mentor Graphics
Presenter: Michael Hochberg, Director, OpSIS, University of Delaware
Suite 5
  • Reliability Checks for Multiple Markets Abstract

    SUITE SESSION Reliability issues usually require design verification driven from circuit schematics to the corresponding layout data. Traditional DRC engines can’t distinguish the specific functions of layout geometries, so manual markers are required to enable automated checks. However, erroneous markers can jeopardize reliability checking. Calibre PERC provides a fully automated and comprehensive EDA design platform to check ESD, latch-up, EOS, ERC and other design issues in both design and stream out databases. Calibre PERC is the first, and currently the only available tool with a qualified design kit from several major foundries for reliability signoff. In this session, to be presented in Mandarin, Mentor Graphics and Semiconductor Manufacturing International Corporation (SMIC) discuss reliability checking with Calibre PERC. Mon 10:00 in Mentor booth.

Presenter: Frank Feng, Circuit Verification Methodologist, Mentor Graphics
Presenter: Hellen Cheng, Senior Manager, IP Development Center, SMIC
Booth 2046
  • Panel: Achieving IC Reliability in High Growth Markets Abstract

    SUITE PANEL Several high growth IC markets are experiencing demand for higher reliability, including mobile/wireless, automotive, industrial control and medical. At the same time, factors such as thinner gate oxide and multiple power rails have the potential to introduce subtle design flaws leading to delayed failure mechanisms. This panel will be an interactive forum where experts and attendees on the show floor can discuss the demand for IC reliability, what design methodologies can reduce the occurrence of delayed failure mechanisms, and how design for reliability checks can be automated to help remove the burden from designers. The panel will be immediately followed by a hosted bar happy hour.

Presenter: Ertugrul Demircan, PVG Manager, Freescale
Moderator: Matthew Hogan, Product Marketing Manager, Calibre Design Solutions, Mentor Graphics
Presenter: Ofer Tamir, Director of Design Enablement and Design Support, TowerJazz
Presenter: Tim Turner, Reliability Center Business Development Manager, College of Nanoscale Science and Engineering, University at Albany, NY
Suite 4
  • Advancing Circuit Reliability at TowerJazz with Calibre PERC Rule Decks Abstract

    SUITE SESSION TowerJazz, the global specialty foundry leader, is now providing Calibre PERC rule decks that enable their customers to perform circuit reliability verification during signoff. TowerJazz provides highly customized electrostatic discharge (ESD) and power management circuit checks based on their specific manufacturing processes. Many of these checks have been automated for the first time by taking advantage of the Calibre PERC product’s unique ability to combine schematic (net list) and physical layout information, which goes beyond the scope of traditional LVS, DRC and ERC tools. This is a one-time, limited seating session for advanced Calibre users. Tue 2:00, Mentor booth.

Presenter: Matthew Hogan, Product Marketing Manager, Calibre Design Solutions, Mentor Graphics
Presenter: Ofer Tamir, Director of Design Enablement and Design Support, TowerJazz
Booth 1746
  • Achieving Best PPA at Advanced Nodes using Olympus-SoC Abstract

    PARTNER KIOSK PRESENTATION One of the predominant P&R challenges is realizing best power, performance and area (PPA), a goal that is more difficult to achieve at advanced nodes due to complex DRC / DFM rules, double patterning, growing design sizes, low power requirements and increasing process and design variations. It is also critical to reduce the die size to justify the cost of moving to smaller nodes. This session shows advanced technologies for efficient design closure such as concurrent PPA optimization, pseudo flat flow methodology and DRC/DP signoff during implementation. Tue 11:00 in the TSMC booth.

Presenter: Arvind Narayanan, Product Marketing Manager, Mentor Graphics
Suite 4
  • Best Practices for 20nm Design Abstract

    SUITE SESSION When leading edge customers first transitioned to 20nm they encountered issues not experienced in prior nodes with the set-up of hardware, flows, and use models during chip verification. TSMC and Mentor worked with these customers to resolve the issues resulting in successful tape-outs of these customers’ designs. TSMC and Mentor will present best practices learned from that experience to help other customers smoothly tape-out their advanced process node designs. Mon 2:00, Mentor booth.

Presenter: John Ferguson, Director of Marketing, Mentor Graphics
Presenter: Yi-Kan Cheng, Deputy Director of the Design Methodology & Kit Development Division, TSMC
Booth 1746
  • Calibre Support for TSMC's 20nm Process Abstract

    PARTNER KIOSK PRESENTATION Mentor will describe advances to support TSMC's 20nm IC processes. Calibre has a new engine with DP anchoring and pre-coloring, DP design rule checking, voltage-dependent checking and patented real-time graphical “error rings” to simplify fixing DP violations. A new 20nm Calibre PERC deck addresses potential reliability issues such as ESD and latch-up. Calibre SmartFill optimizes filling while ensuring that overall run times and files sizes are controlled. The Calibre LFD™ product works with the TSMC Unified DFM Engine, incorporating Calibre Pattern Matching technology to accelerate the litho hot spot detection. Mon 2:30 in the TSMC booth.

Presenter: Michael Buehler-Gracia, Director of Marketing for Calibre Design Solutions, Mentor Graphics