Power management has become a critical aspect of electronic systems design. Driven by customer demand for more functionality and longer battery life in portable electronics, and enabled by advances in process technology, minimizing power consumption is now mandatory. This webinar presents Questa Power Aware Simulation and describes how it is being used today to verify active power management in complex SoC designs. The webinar will explain how IEEE Std 1801 UPF is used to define the power management architecture for a device and how Questa Power Aware simulation enables visualization and debugging of active power management and its effect on design functionality. The webinar will also touch on how other tools within the Questa Verification Platform are used in a comprehensive low power verification flow.