UVM Connect is a new open-source UVM-based library that provides TLM1 and TLM2 connectivity and object passing between SystemC and SystemVerilog UVM models and components. UVM Connect allows you easily to develop integrated verification environments where you take advantage of the strengths of each language to maximize your verification productivity.
Anyone who wants to combine both SystemVerilog UVM and SystemC in a common verification environment should be using UVM Connect. This includes SystemC designers who want to leverage SystemVerilog UVM functionality to add functional coverage and constrained-random stimulus to their verification environment. It also includes SystemVerilog designers who want to use SystemC models as reference models in their environment or any other application that requires components of both languages to run together.