Remember the good old days of connecting the dots? With a bit of common sense and a correct netlist, laying out your board was a snap – heck, even autorouters did a decent job.
Things have gotten a lot more exciting lately, with parallel SERDES interfaces, hierarchical constraints, matched groups, and “virtual pins.” Combined with ridiculous timing margins and lower voltages, now you also have to deal with associated crosstalk and miniscule tolerances.
If there were only a handful of nets, it wouldn’t be so bad – the human brain could deal with that – but when 80% or more of your nets are high-speed, some layout tools should come with a supply of aspirin!
This session will show you how you can avoid the aspirin, using Expedition Enterprise to easily define topologies in the form of constraints, verify that you got them right, and then lay out your board for right-the-first-time results.