This webinar presents Questa Formal Verification and explains how it is being used today, by both designers and verification engineers, to improve design quality and accelerate verification. Automatic checks enable designers to easily qualify code before check-in, without assertions or constraints.
Formal applications use assertion generation and formal verification to quickly and thoroughly verify specific design requirements or tool assumptions that would otherwise be tedious and time-consuming to address. Assertion-based verification enables verification of critical functionality such as control logic to ensure that failures cannot occur. Post-silicon debug using formal verification makes it possible to quickly discover the root cause of an observed failure and confirm that a proposed fix is correct.
The webinar will provide a detailed overview of these capabilities of Questa Formal Verification and the value they bring to functional verification.