On-Demand Web Seminar: Intro to UVM Registers
Who Should View
- Design and Verification Engineers and Managers
What You Will Learn
- How to model registers based on a register specification
- How to create a bus adapter
- How to integrate the register model into your verification environment
- How to write sequences in terms of register transactions
- How to write scoreboards and functional coverage at the register level
Overview
The inclusion of the Register Layer was one of the most requested features of UVM. This session will provide an introduction to the Register Layer and show you how to get started writing tests and sequences and checking results at the register layer. We will also show how to use the UVM Register Layer as a standalone package with OVM2.1.2.